;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page    1
;			     Table of Contents									      /REV=
;
; 1	EBM.MIC -- Conditional Assembly Switches for the behavioral Model
; 2	Revision 1.0
; 28		Revision History
; 34		Conditional Assembly Switches
; 46	REV.MIC -- Microcode Revision Number
; 47	Revision 3.0
; 73		Revision History
; 89		Definition for Microcode Revision Number
; 126		Default for Microcode Patch Number
; 150	DEFINE.MIC -- Microword Definitions for NVAX Microcode
; 151	Revision 1.4
; 189		Revision History
; 279		Defaults for Conditional Assembly Switches
; 301		Introduction
; 315		Microword Formats
; 359		Standard Microinstruction Format
; 1031		Special Microinstruction Format
; 1119		Microsequencer Control Fields
; 1207		Simulation and Assembly Control Fields
; 1371		Validity Checks
; 1414	MACRO.MIC -- Macro Definitions
; 1415	Revision 1.1
; 1441		Revision History
; 1480		ALU Macros
; 1737		MEMREQ Macros
; 1770		SHIFT Macros
; 1873		SPECIAL Macros
; 1890		Q, L, V Field Macros
; 1898		MISC Field Macros
; 1921		Microsequencer Control Macros
; 1934		A/B Select Macros
; 1940		Error Macros
; 1953		Simulator Control Macros
; 1978	ALIGN.MIC -- Hardware Entry Point Assignments
; 1979	Revision 1.0
; 2005		Revision History
; 2061		Exception Dispatches
; 2094		Instruction Dispatches
; 2201	POWERUP.MIC -- Powerup Initialization
; 2202	Revision 1.5
; 2228		Revision History
; 2305		Powerup Initialization
; 2386		Powerup Entry Point
; 2429		Console Halt Entry Point
; 2683	INTEXC.MIC -- Interrupts and Exceptions
; 2684	Revision 1.6
; 2710		Revision History
; 3081		Instruction Dispatch Stall
; 3113		Branch Mispredict Microtrap
; 3157		FPD -- PSL<fpd> Set
; 3400		Double Parameter Exceptions -- Memory Management Fault
; 3738		Single Parameter Exceptions -- Arithmetic Traps and Faults
; 3904		Zero Parameter Exceptions -- Reserved Inst, Addr, Operand; Suspended Vector; Trace; KSNV
; 4090		Hardware Error
; 4152		Machine Check Exception
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page    2
;			     Table of Contents									      /REV=
;
; 4374		Interrupts
; 4820		Interrupt and Exception Handling Subroutines
; 5052		CPU Cleanup Subroutine
; 5257	INTLOGADR.MIC -- Integer, Logical, and Address Class Instructions
; 5258	Revision 1.0
; 5284		Revision History
; 5436		TSTx
; 5477		INCx, DECx
; 5535		CLRx
; 5590		CMPx, BITx
; 5648		ADDin, SUBin, BISxn, BICxn, XORxn, ADWC, SBWC
; 5859		MOVx, MOVAx, MOVZxy, PUSHL, PUSHAx, MCOMx, MNEGx
; 5987		ADAWI
; 6077		CVTBW, CVTBL, CVTWL
; 6135		CVTWB, CVTLB, CVTLW
; 6218		ROTL
; 6264		ASHL
; 6390		ASHQ
; 6593	VFIELD.MIC -- Variable-Length Bit Field Instructions
; 6594	Revision 1.1
; 6620		Revision History
; 6713		FFS, FFC, CMPV, CMPZV, EXTV, EXTZV
; 7241		INSV
; 7627	CTRL.MIC -- Control Instructions
; 7628	Revision 1.0
; 7654		Revision History
; 7739		BRx, Bxx, JMP
; 7836		BSBB, BSBW, JSB
; 7904		RSB
; 7945		CASEx
; 8061		SOBGTR, SOBGEQ
; 8111		AOBLSS, AOBLEQ
; 8167		ACBx
; 8275		BBx, BBxS, BBxC, BBxxI
; 8617		BLBx
; 8663	MULDIV.MIC -- Multiply and Divide Instructions
; 8664	Revision 1.2
; 8690		Revision History
; 8795		MULBn, MULWn, MULLn
; 8967		EMUL
; 9112		DIVBn, DIVWn, DIVLn
; 9359		EDIV
; 9864	CALLRET.MIC -- Procedure Call Instructions
; 9865	Revision 1.1
; 9891		Revision History
; 9981		CALLG, CALLS
; 10429 	RET
; 10740 MISC.MIC -- Miscellaneous Instructions
; 10741 Revision 1.0
; 10767 	Revision History
; 10822 	BPT, XFC
; 10894 	HALT
; 10959 	NOP
; 10998 	INDEX
; 11165 	BICPSW, BISPSW
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page    3
;			     Table of Contents									      /REV=
;
; 11241 	MOVPSL
; 11283 	POPR
; 11516 	PUSHR
; 11738 QUEUE.MIC -- Queue Instructions
; 11739 Revision 1.1
; 11765 	Revision History
; 11859 	INSQUE
; 11952 	REMQUE
; 12069 	INSQxI
; 12605 	REMQxI
; 12967 OPSYS.MIC -- Operating System Support Instructions
; 12968 Revision 1.6
; 12994 	Revision History
; 13175 	CHMx
; 13568 	REI
; 14186 	LDPCTX
; 14545 	SVPCTX
; 14789 	PROBEx
; 15053 	MTPR, MFPR
; 17019 CSTRING.MIC -- Character String Instructions
; 17020 Revision 1.0
; 17046 	Revision History
; 17144 	MOVC3, MOVC5
; 18073 	CMPC3, CMPC5
; 18464 	SCANC, SPANC
; 18695 	LOCC, SKPC
; 18890 	String Packup Routine
; 19054 	String Unpack Routine
; 19277 FPOINT.MIC -- Floating Point Instructions
; 19278 Revision 1.0
; 19305 	Revision History
; 19410 	Floating Point Instructions With Single Bus Operand Transfer
; 19411 		MOVF, MNEGF, CVTFi, CVTiF
; 19412 		CVTiD, CVTFD, CVTiG, CVTFG
; 19473 	Floating Point Instructions With Single Bus Operand Transfer, No Destination Write
; 19474 		TSTF
; 19509 	Floating Point Instructions With Double Bus Operand Transfer
; 19510 		MOVD, MOVG, MNEGD, MNEGG
; 19511 		CVTDi, CVTDF, CVTGi, CVTGF
; 19512 		ADDFx, SUBFx, MULFx, DIVFx
; 19587 	Floating Point Instructions With Double Bus Operand Transfer, No Destination Write
; 19588 		CMPF, TSTD, TSTG
; 19627 	Floating Point Instructions With Quadruple Bus Operand Transfer
; 19628 		ADDDx, SUBDx, MULDx, DIVDx, ADDGx, SUBGx, MULGx, DIVGx, CMPD, CMPG
; 19682 	Floating Point Instructions With Quadruple Bus Operand Transfer -- No destination
; 19683 		CMPD, CMPG
; 19720 VECTOR.MIC -- VAX Vector Instructions
; 19721 Revision 1.0
; 19747 	Revision History
; 19900 	Vector Load Instructions
; 19955 	Vector Store Instructions
; 20010 	Vector Gather Instructions
; 20057 	Vector Scatter Instructions
; 20104 	MFVP
; 20147 	MTVP
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page    4
;			     Table of Contents									      /REV=
;
; 20184 	VSYNC
; 20222 	Vector - Vector Operate Instructions
; 20284 	Longword Vector - Scalar Operate Instructions
; 20333 	Quadword Vector - Scalar Operate Instructions
; 20379 	Vector - Vector Compare Instructions
; 20419 	Longword Vector - Scalar Compare Instructions
; 20458 	Quadword Vector - Scalar Compare Instructions
; 20497 	IOTA
; 20535 EMULATE.MIC -- Emulation Support
; 20536 Revision 1.1
; 20562 	Revision History
; 20703 	Normal Emulation (FPD Clear)
; 21075 	Special Emulation (FPD Set)
; 21174 EBMCODE.MIC -- Behavioral Model Support
; 21175 Revision 1.2
; 21201 	Revision History
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page    5
;	EBM.MIC 	     EBM.MIC -- Conditional Assembly Switches for the behavioral Model			      /REV=
;
				;1	.TOC	"EBM.MIC -- Conditional Assembly Switches for the behavioral Model"
				;2	.TOC	"Revision 1.0"
				;3
				;4	;	Shawn Persels
				;5
;6	.nobin
;7	;****************************************************************************
;8	;*									    *
;9	;*  COPYRIGHT (c) 1988, 1989, 1990, 1991, 1992 BY			    *
;10	;*  DIGITAL EQUIPMENT CORPORATION, MAYNARD, MASSACHUSETTS.		    *
;11	;*  ALL RIGHTS RESERVED.						    *
;12	;*									    *
;13	;*  THIS SOFTWARE IS FURNISHED UNDER A LICENSE AND MAY BE USED AND COPIED   *
;14	;*  ONLY IN  ACCORDANCE WITH  THE  TERMS  OF  SUCH  LICENSE  AND WITH THE   *
;15	;*  INCLUSION OF THE ABOVE COPYRIGHT NOTICE.  THIS SOFTWARE OR ANY  OTHER   *
;16	;*  COPIES THEREOF MAY NOT BE PROVIDED OR OTHERWISE MADE AVAILABLE TO ANY   *
;17	;*  OTHER PERSON.  NO TITLE TO AND OWNERSHIP OF  THE  SOFTWARE IS  HEREBY   *
;18	;*  TRANSFERRED.							    *
;19	;*									    *
;20	;*  THE INFORMATION IN THIS SOFTWARE IS  SUBJECT TO CHANGE WITHOUT NOTICE   *
;21	;*  AND  SHOULD  NOT  BE  CONSTRUED AS	A COMMITMENT BY DIGITAL EQUIPMENT   *
;22	;*  CORPORATION.							    *
;23	;*									    *
;24	;*  DIGITAL ASSUMES NO RESPONSIBILITY FOR THE USE  OR  RELIABILITY OF ITS   *
;25	;*  SOFTWARE ON EQUIPMENT WHICH IS NOT SUPPLIED BY DIGITAL.		    *
;26	;*									    *
;27	;****************************************************************************
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page    6
;	EBM.MIC 	     Revision History									      /REV=
;
;28	.TOC	"	Revision History"
;29
;30	; Edit	  Date	 Who	     Description
;31	; ---- --------- ---	---------------------
;32	; (1)1 17-Jul-90 GMU	Initial production microcode.
;33	; (0)0 16-Aug-88 SDP	Trial microcode.
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page    7
;	EBM.MIC 	     Conditional Assembly Switches							      /REV=
;
;34	.TOC	"	Conditional Assembly Switches"
;35
;36
;37	; The following assignments are used as conditional assembly switches during
;38	; microcode assembly.
;39
;40	.SET/PERF.MODEL=	0		; 1 = include special hooks for the performance model
;41
;42	.SET/BEH.MODEL= 	1		; 1 = include special hooks for the behavioral model
;43
;44
				;45	.bin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page    8
;	REV.MIC 	     REV.MIC -- Microcode Revision Number						      /REV=
;
				;46	.TOC	"REV.MIC -- Microcode Revision Number"
				;47	.TOC	"Revision 3.0"
				;48
				;49	;	Mike Uhler
				;50
;51	.nobin
;52	;****************************************************************************
;53	;*									    *
;54	;*  COPYRIGHT (c) 1990, 1991, 1992 BY					    *
;55	;*  DIGITAL EQUIPMENT CORPORATION, MAYNARD, MASSACHUSETTS.		    *
;56	;*  ALL RIGHTS RESERVED.						    *
;57	;*									    *
;58	;*  THIS SOFTWARE IS FURNISHED UNDER A LICENSE AND MAY BE USED AND COPIED   *
;59	;*  ONLY IN  ACCORDANCE WITH  THE  TERMS  OF  SUCH  LICENSE  AND WITH THE   *
;60	;*  INCLUSION OF THE ABOVE COPYRIGHT NOTICE.  THIS SOFTWARE OR ANY  OTHER   *
;61	;*  COPIES THEREOF MAY NOT BE PROVIDED OR OTHERWISE MADE AVAILABLE TO ANY   *
;62	;*  OTHER PERSON.  NO TITLE TO AND OWNERSHIP OF  THE  SOFTWARE IS  HEREBY   *
;63	;*  TRANSFERRED.							    *
;64	;*									    *
;65	;*  THE INFORMATION IN THIS SOFTWARE IS  SUBJECT TO CHANGE WITHOUT NOTICE   *
;66	;*  AND  SHOULD  NOT  BE  CONSTRUED AS	A COMMITMENT BY DIGITAL EQUIPMENT   *
;67	;*  CORPORATION.							    *
;68	;*									    *
;69	;*  DIGITAL ASSUMES NO RESPONSIBILITY FOR THE USE  OR  RELIABILITY OF ITS   *
;70	;*  SOFTWARE ON EQUIPMENT WHICH IS NOT SUPPLIED BY DIGITAL.		    *
;71	;*									    *
;72	;****************************************************************************
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page    9
;	REV.MIC 	     Revision History									      /REV=
;
;73	.TOC	"	Revision History"
;74
;75	; Edit	  Date	 Who	     Description
;76	; ---- --------- ---	---------------------
;77	; (3)0 06-Jun-91 GMU	Increment revision number to 3 to reflect pass 3 changes.
;78	;    1 01-Feb-91 GMU	Symptom: No mechanism for including a non-standard
;79	;				 patch flag in the source.
;80	;			Cure:	 Default the value MICROCODE.NONSTANDARD to zero
;81	;				 in this module.
;82	; (2)0 21-Jan-91 GMU	Increment revision number to 2 to reflect pass 2 changes.
;83	;
;84	;    1 28-Nov-90 GMU	Symptom: No mechanism for including a microcode
;85	;				 patch number in the source.
;86	;			Cure:	 Default the value of MICROCODE.PATCH
;87	;				 to zero in this module.
;88	; (1)0 17-Jul-90 GMU	Initial production microcode.
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   10
;	REV.MIC 	     Definition for Microcode Revision Number						      /REV=
;
;89	.TOC	"	Definition for Microcode Revision Number"
;90
;91
;92	;	The constant MICROCODE.REVISION is the number returned in bits
;93	;	<7:0> of the SID IPR.  At present, this constant is defined as having
;94	;	the following fields:
;95	;
;96	;		 07 06 05 04 03 02 01
;97	;		+--+--+--+--+--+--+--+
;98	;		|DP|	Edit Number  |
;99	;		+--+--+--+--+--+--+--+
;100	;
;101	;	where:
;102	;
;103	;		DP		= Development/Production flag:
;104	;					0 = Production microcode.
;105	;					1 = Development microcode.
;106	;		Edit Number	= Edit number of the microcode.
;107	;
;108	;	For development microcode, the edit number should be incremented any
;109	;	time a change is made that requires a corresponding model change.
;110	;
;111	;	For production microcode, the edit number should be incremented
;112	;	when any change is made to the microcode.
;113
;114
;115	;	Define the two parts of the microcode revision number.
;116
;117	.SET/MICROCODE.DP.FLAG=0		; development/production flag
;118
;119	.SET/MICROCODE.EDIT.NUMBER=3		; microcode edit number
;120
;121
;122	;	Post-process into the final value
;123
;124	.SET/MICROCODE.REVISION=<.OR[	<.SHIFT[<MICROCODE.DP.FLAG>,7]>,
;125					<MICROCODE.EDIT.NUMBER> 	]>
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   11
;	REV.MIC 	     Default for Microcode Patch Number 						      /REV=
;
;126	.TOC	"	Default for Microcode Patch Number"
;127
;128
;129	;	The constant MICROCODE.PATCH is the number of the last required
;130	;	microcode patch.  It can be thought of as a modifier to the
;131	;	microcode revision number.  The constant MICROCODE.PATCH is
;132	;	defaulted to 0 in this module and may be redefined by assembling
;133	;	the microcode with the REV_PATCH.MIC module.
;134	;
;135	;	The constant MICROCODE.NONSTANDARD is a boolean flag that indicates
;136	;	whether this microcode patch is a normal functional patch
;137	;	release or a non-standard (e.g., performance monitoring) patch.
;138	;	The constant is defaulted to 0 in this module and may be
;139	;	redefined by assembling the microcode with the REV_PATCH.MIC
;140	;	module.
;141
;142	;	Default the microcode patch number and the non-standard
;143	;	patch flag to 0.
;144
;145	.DEFAULT/MICROCODE.PATCH=0
;146
;147	.DEFAULT/MICROCODE.NONSTANDARD=0
;148
				;149	.bin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   12
;    DEFINE.MIC 	     DEFINE.MIC -- Microword Definitions for NVAX Microcode				      /REV=
;
				;150	.TOC	"DEFINE.MIC -- Microword Definitions for NVAX Microcode"
				;151	.TOC	"Revision 1.4"
				;152
				;153	;	Bob Supnik, Mike Uhler
				;154
				;155	;	Assembly directives
				;156
				;157	.ecode
				;158	.hexadecimal
				;159	.rtol
				;160	.allmemfields
				;161	.random
				;162	.width/80				; FAKE machine microword length
				;163	; .width/61				; REAL machine microword length
				;164
;165	.nobin
;166	.nocref
;167
;168	;****************************************************************************
;169	;*									    *
;170	;*  COPYRIGHT (c) 1987, 1988, 1989, 1990, 1991, 1992 BY 		    *
;171	;*  DIGITAL EQUIPMENT CORPORATION, MAYNARD, MASSACHUSETTS.		    *
;172	;*  ALL RIGHTS RESERVED.						    *
;173	;*									    *
;174	;*  THIS SOFTWARE IS FURNISHED UNDER A LICENSE AND MAY BE USED AND COPIED   *
;175	;*  ONLY IN  ACCORDANCE WITH  THE  TERMS  OF  SUCH  LICENSE  AND WITH THE   *
;176	;*  INCLUSION OF THE ABOVE COPYRIGHT NOTICE.  THIS SOFTWARE OR ANY  OTHER   *
;177	;*  COPIES THEREOF MAY NOT BE PROVIDED OR OTHERWISE MADE AVAILABLE TO ANY   *
;178	;*  OTHER PERSON.  NO TITLE TO AND OWNERSHIP OF  THE  SOFTWARE IS  HEREBY   *
;179	;*  TRANSFERRED.							    *
;180	;*									    *
;181	;*  THE INFORMATION IN THIS SOFTWARE IS  SUBJECT TO CHANGE WITHOUT NOTICE   *
;182	;*  AND  SHOULD  NOT  BE  CONSTRUED AS	A COMMITMENT BY DIGITAL EQUIPMENT   *
;183	;*  CORPORATION.							    *
;184	;*									    *
;185	;*  DIGITAL ASSUMES NO RESPONSIBILITY FOR THE USE  OR  RELIABILITY OF ITS   *
;186	;*  SOFTWARE ON EQUIPMENT WHICH IS NOT SUPPLIED BY DIGITAL.		    *
;187	;*									    *
;188	;****************************************************************************
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   13
;    DEFINE.MIC 	     Revision History									      /REV=
;
;189	.TOC	"	Revision History"
;190
;191	; Edit	  Date	 Who	     Description
;192	; ---- --------- ---	---------------------
;193	;    4 24-Jul-91 JFB	Symptom: No symbolic constant defined for PCSTS
;194	;			Cure:	 Add IPR.PCSTS
;195	;    3 20-Feb-91 GMU	Symptom: No symbolic constant defined for P1BR and P1LR
;196	;				 bias values.
;197	;			Cure:	 Add P1BR.BIAS, P1LR.BIAS.SHIFTED, P1LR.BIAS.UNSHIFTED.
;198	;    2 28-Jan-91 GMU	Symptom: No symbolic definition for PCSCR PCS enable bit.
;199	;			Cure:	 Add PCSCR.PCS.ENB.
;200	;			Symptom: There is no easy way to extract the microcode
;201	;				 non-standard patch flag from the .ULD/.ULA file.
;202	;			Cure:	 Include the UCODE.NONSTANDARD value in the CONST
;203	;				 field and equate it to the MICROCODE.NONSTANDARD
;204	;				 constant.
;205	;    1 28-Nov-90 GMU	Symptom: There is no easy way to extract the microcode
;206	;				 revision number and the microcode
;207	;				 patch number from the .ULD/.ULA file.
;208	;			Cure:	 Include the UCODE.REVISION and UCODE.PATCH
;209	;				 values in the CONST field and equate them
;210	;				 to the MICROCODE.REVISION and MICROCODE.PATCH
;211	;				 constants.  This allows a program to find the
;212	;				 values by parsing the symbol table at the
;213	;				 end of the .ULD/.ULA.
;214	; (1)0 31-Jul-90 GMU	Initial production microcode.
;215	;
;216	; Begin version 1.0 here
;217	;   48 31-Jul-90 JFB	Add test pins to SEQ.COND/VECTOR field,
;218	;			and create SEQ.COND/TEST_PINS synonym.
;219	;   47 01-Jul-90 GMU	Add MCHK.PMF.CONFIG, SCB.PMF.BASE, ECR bit definitions.
;220	;   46 25-Jun-90 GMU	PCSCR turned out to be read/write after all, so back out
;221	;			edit 41.
;222	;   45 11-Jun-90 GMU	Renumber CPUSTATE registers in A and DST field to match
;223	;			implementation.
;224	;   44 11-Jun-90 GMU	Add MISC/INCR.PERF.COUNT decode.
;225	;   43 06-Jun-90 GMU	More of edit 42.
;226	;   42 05-Jun-90 GMU	Reorder SEQ.COND decodes for implementation.
;227	;   41 08-May-90 GMU	Remove PCSCR as a source in the A field (it is a write-
;228	;			only register).
;229	;   40 01-May-90 GMU	Note that last machine check code is included in ASTLVL.
;230	;   39 23-Apr-90 GMU	Remove artifact for an external vector unit interface.
;231	;   38 12-Apr-90 GMU	Add performance monitoring facility decodes.
;232	;   37 30-Mar-90 GMU	Add validity checks to restrict use of DST field
;233	;			for read-type MRQ commands.
;234	;   36 18-Mar-90 GMU	Rename JTAGCR to PCSCR.
;235	;   35 28-Feb-90 GMU	Remove FBOX.FAULT.CODE.
;236	;   34 23-Feb-90 GMU	Add new CONST.10 constants for MxPR rewrite, remove MXPR
;237	;			constant decodes on the A bus.
;238	;   33 20-Feb-90 GMU	Remove obsolete ALU, MISC, MISC1, and SEQ.COND decodes.
;239	;   32 12-Feb-90 GMU	Add MISC/SIM.IE.INTEXC directive for use in the behavioral
;240	;			model.
;241	;   31 19-Jan-90 GMU	Change definition of K.MXPR.0.31 definition to include
;242	;			bit for CPUID IPR.
;243	;   30 19-Jan-90 GMU	Add IPR.CEFSTS and CEFSTS.RDLK definitions.
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   14
;    DEFINE.MIC 	     Revision History									      /REV=
;
;244	;   29 19-Jan-90 GMU	Remove VMPSL, add CPUID to ASTLVL comment.
;245	;   28 18-Jan-90 GMU	Add SEQ.COND/FBOX.FAULT.CODE.
;246	;   27 16-Jan-90 DGM	Change SEQ.COND field queue decode.  Update comments.
;247	;   26 15-Jan-90 GMU	Add MISC/CLR.VECT.RDY decode.
;248	;   25 09-Jan-90 GMU	Add ISR bit definitions.
;249	;   24 02-Jan-90 GMU	Remove bogus vector opcode and status decodes.
;250	;   23 21-Dec-89 GMU	Add IPR.CACHE definition.
;251	;   22 06-Dec-89 GMU	Continue cleanup.
;252	;   21 01-Dec-89 GMU	Add IPR.ICCS to CONST.10 field.
;253	;   20 17-Nov-89 GMU	Cleanup comments, remove obsolte decodes, note those
;254	;			that should be removed in the future.
;255	;   19 16-Nov-89 GMU	Add ALU/A.MINUS.B.MINUS.1 and B/K.FFFF; remove
;256	;			A/TEMP and DST/TEMP.
;257	;   18 07-Nov-89 GMU	Add new machine check codes.
;258	;   17 03-Nov-89 GMU	Add PSL.TP constant.
;259	;   16 23-Oct-89 GMU	Add PTE.M constant.
;260	;   15 18-Oct-89 GMU	Include validity check in use of FLUSH.PAQ to require
;261	;			MRQ request.
;262	;   14 21-Sep-89 GMU	Add PSL.B0 to DST field.
;263	;   13 11-Sep-89 GMU	Add JTAGCR to A and DST fields; add PROBE.V.RCHK.NOFILL
;264	;			to MRQ field.
;265	;   12 31-Aug-89 GMU	Update Cbox IPR assignments.
;266	;   11 23-Aug-89 GMU	Combine Fbox operand valid decodes into one decode.
;267	;   10 22-Aug-89 GMU	Add TB.TAG.FILL and TB.PTE.FILL commands to MRQ field.
;268	;    9 16-Aug-89 GMU	Remove CLEAR.WRITE.BUFFERS and READ.INT.VECTOR from
;269	;			MRQ field.
;270	;    8 14-Aug-89 GMU	Add new K.MXPR.x constants, rename old ones.
;271	;    7 26-Jul-89 GMU	Change Ibox IPR constant definitions from Cx to Dx.
;272	;    6 19-Jul-89 GMU	Add ECR, ESR to DST, A fields.
;273	;    5 12-Jul-89 GMU	Updated IPR encodings.
;274	;    4 30-Jun-89 DGM	Added FBOX.DISABLED microbranch condition
;275	;    3 08-Feb-89 GMU	Remove C bit.
;276	;    2 22-Nov-88 DB	Add MISC3/F.DEST.CHECK
;277	;    1 23-Aug-88 GMU	Add PM hooks for CASEx.
;278	; (0)0 27-Aug-87 RMS	Trial microcode.
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   15
;    DEFINE.MIC 	     Defaults for Conditional Assembly Switches 					      /REV=
;
;279	.TOC	"	Defaults for Conditional Assembly Switches"
;280
				;281	.bin
				;282
				;283	;	The following assignments specify conditional assembly switches for the
				;284	;	microcode assembly.  They are specified as defaults here, and may be
				;285	;	redefined earlier in the assembly (in Exx.MIC) with explicit
				;286	;	.SET directives.
				;287
				;288	.DEFAULT/PERF.MODEL=	0	; 1 = include special hooks for the performance model
				;289					; 0 = exclude special hooks for the performance model
				;290
				;291	.DEFAULT/BEH.MODEL=	0	; 1 = include special hooks for the behavioral model
				;292					; 0 = exclude special hooks for the behavioral model
				;293
				;294	;	The following definitions post process those above and should never be
				;295	;	changed alone.
				;296
				;297	.SET/NOT.PERF.MODEL=<.NOT[ <PERF.MODEL>]> ; logical complement for use in validity checks
				;298	.SET/NOT.BEH.MODEL=<.NOT[ <BEH.MODEL>]>   ; logical complement for use in validity checks
				;299
;300	.nobin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   16
;    DEFINE.MIC 	     Introduction									      /REV=
;
;301	.TOC	"	Introduction"
;302
;303	;	The NVAX microword consists of 61 bits divided into two major sections.
;304	;	Bits <60:15> control the data path and are encoded into two formats.
;305	;	Bits <14:0> control the microsequencer and are encoded into two formats.
;306	;
;307	;	In addition to the bits in the real microword, there are additional
;308	;	bits defined which provide assembly-time validity checking for the
;309	;	microcode, plus support for data-dependent decisions in the performance
;310	;	model.	The additional bits are stripped out by the allocator during
;311	;	pass 3 of the allocation process.
;312	;
;313	;	The formats are defined in the Microinstruction Formats Chapter of the NVAX
;314	;	CPU Functional Specification.
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   17
;    DEFINE.MIC 	     Microword Formats									      /REV=
;
;315	.TOC	"	Microword Formats"
;316
;317	;	The microword formats on this page represent the final microword after
;318	;	post-processing by the allocator.
;319	;
;320	;	Data path control, standard format
;321	;
;322	;	 6|5 5 5 5|5 5 5 5|5 5 4 4|4 4 4 4|4 4 4 4|3 3 3 3|3 3 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1
;323	;	 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5
;324	;	+-+---------+---------+-+-----+-+---------+---------+-+-+-+-----------+-----------+---------+
;325	;	|0|   ALU   |	MRQ   |Q| SHF |0|   VAL   |    B    |L|W|V|    DST    |     A	  |  MISC   |
;326	;	+-+---------+---------+-+-----+-+---------+---------+-+-+-+-----------+-----------+---------+
;327	;				      |1|POS|	 CONST	    | MISC not equal CONST.10
;328	;				      +-+---+---------------+
;329	;				      |1|     CONST.10	    | MISC equal CONST.10
;330	;				      +-+-------------------+
;331	;
;332	;	Data path control, special format
;333	;
;334	;	 6|5 5 5 5|5 5 5 5|5 5 4 4|4 4 4 4|4 4 4 4|3 3 3 3|3 3 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1
;335	;	 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5
;336	;	+-+---------+---------+-------+-+-------+-+---------+-+-+-+-----------+-----------+---------+
;337	;	|1|   ALU   |	MRQ   | MISC1 |0| MISC2 |D|    B    |L|W|V|    DST    |     A	  |  MISC   |
;338	;	+-+---------+---------+-------+-+-------+-+---------+-+-+-+-----------+-----------+---------+
;339	;				      |1|POS|	 CONST	    | MISC not equal CONST.10
;340	;				      +-+---+---------------+
;341	;				      |1|     CONST.10	    | MISC equal CONST.10
;342	;				      +-+-------------------+
;343	;
;344	;	Microsequencer control, jump format
;345	;
;346	;	 1 1 1|1 1    |       |
;347	;	 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
;348	;	+-+-+---+---------------------+
;349	;	|0|S|MUX|	   J	      |
;350	;	+-+-+---+---------------------+
;351	;
;352	;	Microsequencer control, branch format
;353	;
;354	;	 1 1 1|1 1    |       |
;355	;	 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
;356	;	+-+-+---------+---------------+
;357	;	|1|S|SEQ.COND |    BR.OFF     |
;358	;	+-+-+---------+---------------+
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   18
;    DEFINE.MIC 	     Standard Microinstruction Format							      /REV=
;
;359	.TOC	"	Standard Microinstruction Format"
;360
;361	;	The fields for the standard microinstruction are:
;362	;
;363	;	FORMAT/ 	STANDARD
;364	;	ALU/		ALU operation
;365	;	MRQ/		Mbox request
;366	;	Q/		Q latch update control
;367	;	SHF/		Shift operation
;368	;	LIT/		B operand control, as follows:
;369	;	    LIT/0:
;370	;		VAL/	Shift count value
;371	;		B/	B port select
;372	;	    LIT/1:
;373	;		POS/	Contant position	\ If MISC field does not
;374	;		CONST/	8-bit constant value	/ contain CONST.10.BIT
;375	;		CONST.10/ 10-bit constant value   If MISC field contains CONST.10.BIT
;376	;	L/		Length control
;377	;	W/		Wbus driver control
;378	;	V/		VA latch update control
;379	;	DST/		Wbus destination
;380	;	A/		ALU A port select
;381	;	MISC/		Miscellaneous
;382
;383	;	This field defines foramt of the current microinstruction.
;384
;385	FORMAT/=<60>,.DEFAULT=<FORMAT/STANDARD>
;386
;387		STANDARD		=  0	; select the standard format
;388		SPECIAL 		=  1	; select the special format
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   19
;    DEFINE.MIC 	     Standard Microinstruction Format							      /REV=
;
;389
;390	;	Standard microinstruction format, continued.
;391
;392	;	This field defines the ALU operation.  Inputs to the ALU are selected by the A and B field decodes.
;393	;	The output of the ALU can drive the VA (based on V control) and/or the Wbus (based on W control).
;394	;	The ALU condition codes are length dependent (based on DL and L control) and can drive the PSL logic
;395	;	(based on W control).
;396
;397	ALU/=<59:55>,.DEFAULT=<ALU/0>
;398
;399	;		Function	  Val		Operation			  Comments and restrictions
;400	;	-----------------------  ----	---------------------------	----------------------------------------------------
;401		PASS.A			=  00	; A
;402		PASS.B			=  01	; B
;403	;				=  02
;404	;				=  03
;405	;				=  04
;406	;				=  05
;407	;				=  06
;408	;				=  07
;409		A.AND.B 		=  08	; A .AND. B
;410		A.AND.NOT.B		=  09	; A .AND. (.NOT. B)
;411		A.OR.B			=  0A	; A .OR. B
;412	;				=  0B
;413		A.XOR.B 		=  0C	; A .XOR. B
;414		NOT.A.AND.B		=  0D	; (.NOT. A) AND B
;415	;				=  0E
;416		A.MINUS.B.MINUS.1	=  0F	; A - B - 1			A + (.NOT. B)
;417
;418		A.PLUS.1		=  10	; A + 1
;419		A.PLUS.B		=  11	; A + B
;420		A.PLUS.B.PLUS.1 	=  12	; A + B + 1
;421	;				=  13
;422		B.MINUS.A		=  14	; B - A 			B + (.NOT. A) + 1
;423		A.MINUS.B		=  15	; A - B 			A + (.NOT. B) + 1
;424		A.MINUS.1		=  16	; A - 1
;425	;				=  17
;426		A.PLUS.4		=  18	; A + 4
;427		A.MINUS.4		=  19	; A - 4
;428		NEG.B			=  1A	; -B
;429		NOT.B			=  1B	; ~B
;430		SMUL.STEP		=  1C	; signed multiply step
;431		UDIV.STEP		=  1D	; unsigned divide step
;432	;				=  1E
;433	;				=  1F
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   20
;    DEFINE.MIC 	     Standard Microinstruction Format							      /REV=
;
;434
;435	;	Standard microinstruction format, continued.
;436
;437	;	This field defines the memory request function.  The address source is either the VA register, or if VA
;438	;	is updated from the ALU output, the ALU.  On reads, the DST field supplies the destination (must be
;439	;	a working register or a general register).  On writes, the shifter supplies the write data.
;440
;441	MRQ/=<54:50>,.DEFAULT=<MRQ/NOP>
;442
;443	;	       Command		 Val	Validity checks 	Description		Type	Check	Mode
;444	;	-----------------------  --- -------------------------- -----------------------+-------+-------+---------
;445		NOP			= 00				; no op 		none	none	none
;446		SYNC.BDISP		= 01				; no op to Mbox 	none	none	none
;447									; S4: stall if branch queue entry not valid
;448		SYNC.BDISP.RETIRE	= 02,.VALIDITY=<MUX.LAST>	; no op to Mbox 	none	none	none
;449									; S4: stall if branch queue entry not valid
;450									; S5: retire branch queue entry
;451		SYNC.BDISP.TEST.PRED	= 03,.VALIDITY=<MUX.LAST>	; no op to Mbox 	none	none	none
;452									; S4: stall if branch queue entry not valid
;453									; S5: retire branch queue entry, evaluate branch
;454									;     prediction, trap if incorrect
;455		TB.INVALIDATE.SINGLE	= 04				; TB invalidate single
;456		TB.INVALIDATE.PROCESS	= 05				; TB invalidate process
;457		TB.INVALIDATE.ALL	= 06				; TB invalidate all
;458	;				= 07
;459
;460		SYNC.MBOX		= 08				; synchronize with previous M-box command
;461		LOAD.PC 		= 09				; Send new PC to Ibox via Mbox
;462		TB.TAG.FILL		= 0A				; Send new TB tag to Mbox
;463		TB.PTE.FILL		= 0B				; Send new TB PTE to Mbox
;464
;465	;				= 0C
;466	;				= 0D
;467	;				= 0E
;468	;				= 0F
;469
;470		READ.V.RCHK		= 10,.VALIDITY=<DST.WN.OR.RN>	; read			virt	read	current
;471		READ.V.WCHK		= 11,.VALIDITY=<DST.WN.OR.RN>	; read with write check virt	write	current
;472		READ.V.NOCHK		= 12,.VALIDITY=<DST.WN.OR.RN>	; read with no check	virt	none	none
;473		READ.V.LOCK		= 13,.VALIDITY=<DST.WN> 	; read lock		virt	write	current
;474		READ.P			= 14,.VALIDITY=<DST.WN.OR.RN>	; read physical 	phys	none	none
;475		READ.PR 		= 15,.VALIDITY=<DST.WN> 	; read PR		phys	none	none
;476		PROBE.V.RCHK.NOFILL	= 16,.VALIDITY=<DST.WN> 	; read probe no fill	virt	read	mode
;477		PROBE.V.RCHK		= 17,.VALIDITY=<DST.WN> 	; read probe byte	virt	read	mode
;478
;479		WCHK			= 18				; write check		virt	write	current
;480		WRITE.V.WCHK		= 19				; write 		virt	write	current
;481		WRITE.V.NOCHK		= 1A				; write with no check	virt	none	none
;482		WRITE.V.UNLOCK		= 1B				; write unlock		virt	write	current
;483		WRITE.P 		= 1C				; write physical	phys	none	none
;484		WRITE.PR		= 1D				; write PR		phys	none	none
;485	;				= 1E
;486		PROBE.V.WCHK		= 1F,.VALIDITY=<DST.WN.OR.RN>	; write probe byte	virt	write	mode
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   21
;    DEFINE.MIC 	     Standard Microinstruction Format							      /REV=
;
;487
;488	;	Standard microinstruction format, continued.
;489	;
;490	;	These field defines the shift operation.  Inputs to the shifter are selected by the A and B field
;491	;	decodes.  If the B port selects a literal, the shift count is supplied by SC;  otherwise, it can
;492	;	be supplied either by SC or the count field.  The output of the shifter can drive the Wbus (based
;493	;	on W control); based on Q control, it is conditionally latched in the Q (shift output) register.
;494	;	The shifter condition codes are always longword and can drive the PSL logic (based on W control).
;495
;496	Q/=<49>,.DEFAULT=<Q/HOLD.Q>
;497
;498		HOLD.Q			=  0	; maintain current value of Q
;499		UPDATE.Q		=  1	; update Q from shifter output
;500
;501	SHF/=<48:46>,.DEFAULT=<SHF/NOP>
;502
;503	;		Function	  Val		Operation			  Comments and restrictions
;504	;	-----------------------  ----	---------------------------	----------------------------------------------------
;505		NOP			=  0	; none				SHIFT.SIGN is preserved
;506		PASS.A			=  1	; output = A
;507		PASS.B			=  2	; output = B
;508		PASS.Z			=  3	; output = 0
;509		LEFT.DOUBLE		=  4	; output = A'B lsh count
;510		LEFT.SINGLE		=  5	; output = A'0 lsh count
;511		RIGHT.DOUBLE		=  6	; output = A'B rsh count
;512		RIGHT.SINGLE		=  7	; output = 0'B rsh count
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   22
;    DEFINE.MIC 	     Standard Microinstruction Format							      /REV=
;
;513
;514	;	Standard microinstruction format, continued.
;515
;516	;	This field specifies the B port select.  The B port select can either be a literal constant
;517	;	(in which case the shift count is always supplied by SC), or a register select (in which
;518	;	case the shift count can be supplied either by SC or by the shift value field).
;519
;520	LIT/=<45>,.DEFAULT=<LIT/BREG>
;521
;522		BREG			=  0	; B port select is a B field register
;523		LIT			=  1	; B port select is a literal constant
;524
;525	;	When LIT specifies a literal constant, this field, along with the MISC/CONST.10.BIT decode
;526	;	selects the position of the constant.  If the MISC field does not contain the MISC/CONST.10.BIT
;527	;	decode, the POS field selects the byte position within the longword of the 8-bit constant
;528	;	specified by the CONST field.  If the MISC field contains the MISC/CONST.10.BIT decode,
;529	;	the POS and CONST fields are concatenated to supply a 10-bit constant which is placed in
;530	;	bits <9:0> of the B bus.  In either case, all remaining bits of the longword are forced to zero.
;531
;532	POS/=<44:43>,.DEFAULT=<POS/0>
;533
;534	;	Selection		  Val	    Resulting constant
;535	;	---------		 ----	-------------------------
;536		BYTE0			=  00	; 000000cc  (bits <7:0>)
;537		BYTE1			=  01	; 0000cc00  (bits <15:8>)
;538		BYTE2			=  02	; 00cc0000  (bits <23:16>)
;539		BYTE3			=  03	; cc000000  (bits <31:24>)
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   23
;    DEFINE.MIC 	     Standard Microinstruction Format							      /REV=
;
;540
;541	;	Standard microinstruction format, continued.
;542
;543	;	When LIT specifies a literal constant and the MISC field does not contain the
;544	;	MISC/CONST.10.BIT decode, this field supplies the 8-bit constant value.
;545
;546	CONST/=<42:35>,.DEFAULT=<CONST/0>
;547
;548	;	    Constant		  Val		Interpretation or use
;549	;	-----------------------  ----	-----------------------------------------------
;550	;	System ID.
;551
;552		NVAX.SID		= 19.	; system ID (byte 3)
;553
;554	;	Revision constants (here so that they appear in the .ULD/.ULA symbol table)
;555
;556		UCODE.REVISION		= <MICROCODE.REVISION> ; Microcode revision number
;557		UCODE.PATCH		= <MICROCODE.PATCH> ; Microcode patch number
;558		UCODE.NONSTANDARD	= <MICROCODE.NONSTANDARD> ; Microcode non-standard patch
;559
;560	;	SCB offsets.
;561
;562		SCB.MACHCHK		= 004	; SCB vector, machine check
;563		SCB.KSNV		= 008	; SCB vector, kernel stack not valid
;564		SCB.PWRFL		= 00C	; SCB vector, power fail
;565		SCB.RESPRIV		= 010	; SCB vector, reserved/priv instruction
;566		SCB.XFC 		= 014	; SCB vector, XFC instruction
;567		SCB.RESOP		= 018	; SCB vector, reserved operand
;568		SCB.RESADD		= 01C	; SCB vector, reserved addressing mode
;569		SCB.ACV 		= 020	; SCB vector, access control violation
;570		SCB.TNV 		= 024	; SCB vector, translation not valid
;571		SCB.TP			= 028	; SCB vector, trace pending
;572		SCB.BPT 		= 02C	; SCB vector, breakpoint trace
;573		SCB.ARITH		= 034	; SCB vector, arithmetic fault
;574		SCB.VM			= 038	; SCB vector, VM trap
;575		SCB.MODIFY		= 03C	; SCB vector, modify fault
;576		SCB.CHMK		= 040	; SCB vector, change mode to kernel
;577		SCB.CHME		= 044	; SCB vector, change mode to executive
;578		SCB.CHMS		= 048	; SCB vector, change mode to supervisor
;579		SCB.CHMU		= 04C	; SCB vector, change mode to user
;580		SCB.SERR		= 054	; SCB vector, soft error interrupt
;581		SCB.PMF.BASE		= 058	; SCB vector, physical address of performance monitoring facility block
;582		SCB.HERR		= 060	; SCB vector, hard error interrupt
;583		SCB.VECT.DISABLED	= 068	; SCB vector, vector unit disabled exception
;584		SCB.IPLSOFT		= 080	; SCB vector, software interrupts
;585		SCB.INTTIM		= 0C0	; SCB vector, interval timer interrupt
;586		SCB.EMULATE		= 0C8	; SCB vector, emulation
;587		SCB.EMULFPD		= 0CC	; SCB vector, emulation with FPD set
;588
;589	;	Arithmetic trap and fault codes.
;590
;591		ARITH.TRAP.INTOVF	=  01	; integer overflow
;592		ARITH.TRAP.INTDIV	=  02	; integer divide-by-zero
;593		ARITH.TRAP.SUBRNG	=  07	; subscript range
;594		ARITH.FAULT.FLTOVF	=  08	; floating overflow
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   24
;    DEFINE.MIC 	     Standard Microinstruction Format							      /REV=
;
;595		ARITH.FAULT.FLTDIV	=  09	; floating divide-by-zero
;596		ARITH.FAULT.FLTUND	=  0A	; floating underflow
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   25
;    DEFINE.MIC 	     Standard Microinstruction Format							      /REV=
;
;597
;598	;	Standard microinstruction format, continued.
;599	;	CONST field, continued.
;600
;601	;	    Constant		  Val		Interpretation or use
;602	;	-----------------------  ----	-----------------------------------------------
;603	;	Console halt codes.
;604
;605		ERR.HLTPIN		=  02	; HALT_L pin asserted
;606		ERR.PWRUP		=  03	; initial power up
;607		ERR.INTSTK		=  04	; interrupt stack not valid
;608		ERR.DOUBLE		=  05	; machine check during exception processing
;609		ERR.HLTINS		=  06	; HALT instruction in kernel mode
;610		ERR.ILLVEC		=  07	; illegal SCB vector (bits <1:0> = 11)
;611		ERR.WCSVEC		=  08	; WCS SCB vector (bits <1:0> = 10)
;612		ERR.CHMFI		=  0A	; CHMx on interrupt stack
;613		ERR.IE0 		=  10	; ACV/TNV during machine check processing
;614		ERR.IE1 		=  11	; ACV/TNV during kernel-stack-not-valid processing
;615		ERR.IE2 		=  12	; machine check during machine check processing
;616		ERR.IE3 		=  13	; machine check during kernel-stack-not-valid processing
;617		ERR.IE.PSL.26-24.101	=  19	; PSL<26:24> = 101 during interrupt or exception
;618		ERR.IE.PSL.26-24.110	=  1A	; PSL<26:24> = 110 during interrupt or exception
;619		ERR.IE.PSL.26-24.111	=  1B	; PSL<26:24> = 111 during interrupt or exception
;620		ERR.REI.PSL.26-24.101	=  1D	; PSL<26:24> = 101 during REI
;621		ERR.REI.PSL.26-24.110	=  1E	; PSL<26:24> = 110 during REI
;622		ERR.REI.PSL.26-24.111	=  1F	; PSL<26:24> = 111 during REI
;623
;624	;	Machine check codes.
;625
;626		MCHK.UNKNOWN.MSTATUS	=  01	; unknown memory management status
;627		MCHK.INT.ID.VALUE	=  02	; unknown interrupt id
;628		MCHK.CANT.GET.HERE	=  03	; unknown microcode dispatch
;629		MCHK.MOVC.STATUS	=  04	; unknown MOVCx status
;630		MCHK.ASYNC.ERROR	=  05	; async HW error microtrap
;631		MCHK.SYNC.ERROR 	=  06	; sync HW error microtrap
;632		MCHK.PMF.CONFIG 	=  07	; performance monitoring facility incorrectly configured
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   26
;    DEFINE.MIC 	     Standard Microinstruction Format							      /REV=
;
;633
;634	;	Standard microinstruction format, continued.
;635	;	CONST field, continued.
;636
;637	;	    Constant		  Val		Interpretation or use
;638	;	-----------------------  ----	-----------------------------------------------
;639	;	PTE bits
;640
;641		PTE.M			=  04	; PTE<M> (byte 3)
;642
;643	;	PSL bits
;644
;645		PSL.TP			=  40	; PSL<TP> (byte 3)
;646
;647	;	ISR bit definitions
;648
;649		ISR.HALT		=  80	; ISR bit to clear HALT_L flop (byte 3)
;650		ISR.SERR		=  08	; ISR bit to clear SERR_L flop (byte 3)
;651		ISR.PMF 		=  10	; ISR bit to clear PMF flop (byte 3)
;652		ISR.INT_TIM		=  01	; ISR bit to clear INT_TIM_L flop (byte 3)
;653		ISR.CLEAR.ALL		=  0F9	; ISR mask to clear all interrupt requests and ICCS<6> (byte 3)
;654
;655	;	ECR bit definitions
;656
;657		ECR.ICCS.EXT		=  80	; ECR bit that indicates external ICCS (byte 0)
;658		ECR.PMF.ENABLE		=  01	; ECR bit that enables the PMF (byte 2)
;659		ECR.PMF.CLEAR		=  80	; virtual ECR bit that clears the PMF counters (byte 3)
;660
;661	;	PCSCR bit definitions
;662
;663		PCSCR.PCS.ENB		= 02	; PCSCR bit that indicates that PCS is enabled (byte 1)
;664
;665	;	CEFSTS bit definitions
;666
;667		CEFSTS.RDLK		=  01	; CEFSTS bit to clear RDLK error (byte 0)
;668
;669	;	PCCTL bit definitions
;670
;671		PCCTL.FORCE.HIT 	=  07	; Force hit+I enable+D enable (byte 0)
;672
;673	;	IPR mask bits and right-justified encodings
;674
;675		IPR.CACHE		=  01	; Bit in byte 3 which differentiates cache IPRs from normal IPRs.
;676		IPR.EBOX.BLOCK		=  78	; First of 8 special-cased Ebox IPRs
;677		IPR.VECTOR.BLOCK	=  90	; First of 8 special-cased vector IPRs
;678
;679	;	P1BR bias constant
;680
;681		P1BR.BIAS		=  80	; P1BR bias constant (byte 2)
;682		P1LR.BIAS.SHIFTED	=  40	; P1LR bias constant (byte 3 of shifted value)
;683		P1LR.BIAS.UNSHIFTED	=  20	; P1LR bias constant (byte 2 of unshifted value)
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   27
;    DEFINE.MIC 	     Standard Microinstruction Format							      /REV=
;
;684
;685	;	Standard microinstruction format, continued.
;686	;	CONST.10 field
;687
;688	;	When LIT specifies a literal constant and the MISC field contains the
;689	;	MISC/CONST.10.BIT decode, this field supplies the 10-bit constant value.
;690	;	Note that this field overlaps the POS and CONST fields, and is only
;691	;	used when the MISC field contains the MISC/CONST.10.BIT decode.
;692
;693	CONST.10/=<44:35>
;694
;695	;	    Constant		  Val		Interpretation or use
;696	;	-----------------------  ----	-----------------------------------------------
;697	;	Internal processor registers.  These values are pre-shifted by 2 bits to
;698	;	position then into bits <9:2> rather than <7:0>.
;699
;700		IPR.ICCS		= <.SHIFT[<018>,2]> ; External ICCS register
;701
;702		IPR.IAK.BASE		= <.SHIFT[<.DIFF[<040>,<014>]>,2]>
;703							    ; interrupt IAK base (IPR.IAK.BASE+[IPL*4] = IPR.IAK1x)
;704		IPR.CWB 		= <.SHIFT[<044>,2]> ; Clear write buffers
;705
;706		IPR.CEFSTS		= <.SHIFT[<0AC>,2]> ; Cbox CEFSTS register address
;707
;708
;709		IPR.BPCR		= <.SHIFT[<0D4>,2]> ; Ibox branch prediction control register
;710		IPR.BPC 		= <.SHIFT[<0D6>,2]> ; Ibox backup PC
;711		IPR.BPC.UNWIND		= <.SHIFT[<0D7>,2]> ; Ibox backup PC with RLOG unwind
;712
;713		IPR.MP0BR		= <.SHIFT[<0E0>,2]> ; Mbox P0 base register
;714		IPR.MP0LR		= <.SHIFT[<0E1>,2]> ; Mbox P0 length register
;715		IPR.MP1BR		= <.SHIFT[<0E2>,2]> ; Mbox P1 base register
;716		IPR.MP1LR		= <.SHIFT[<0E3>,2]> ; Mbox P1 length register
;717		IPR.MSBR		= <.SHIFT[<0E4>,2]> ; Mbox system base register
;718		IPR.MSLR		= <.SHIFT[<0E5>,2]> ; Mbox system length register
;719		IPR.MMAPEN		= <.SHIFT[<0E6>,2]> ; Mbox memory management enable
;720		IPR.PAMODE		= <.SHIFT[<0E7>,2]> ; Mbox physical address mode
;721		IPR.MMEADR		= <.SHIFT[<0E8>,2]> ; Mbox MME address
;722		IPR.MMEPTE		= <.SHIFT[<0E9>,2]> ; Mbox MME PTE address
;723		IPR.MMESTS		= <.SHIFT[<0EA>,2]> ; Mbox MME status
;724		IPR.PCSTS		= <.SHIFT[<0F4>,2]> ; Mbox Pcache status
;725		IPR.PCCTL		= <.SHIFT[<0F8>,2]> ; Mbox Pcache control
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   28
;    DEFINE.MIC 	     Standard Microinstruction Format							      /REV=
;
;726
;727	;	Standard microinstruction format, continued.
;728
;729	;	When the LIT field specifies a B register and shift value, the shift count is
;730	;	taken from this field.	A zero value specifies a shift by SC.
;731
;732	VAL/=<44:40>,.DEFAULT=<VAL/0>
;733
;734	;	When the LIT field specifies a B register and shift value, this field supplies the
;735	;	B port decode.
;736
;737	B/=<39:35>,.DEFAULT=<B/NONE>
;738
;739	;		Function	  Val		     Operation				    Comments
;740	;	-----------------------  ----	--------------------------------------- --------------------------------------------
;741		NONE			=  00	; No source
;742		W0			=  01	; working register 0
;743		W1			=  02	; working register 1
;744		W2			=  03	; working register 2
;745		W3			=  04	; working register 3
;746		W4			=  05	; working register 4
;747		W5			=  06	; working register 5
;748	;				=  07
;749
;750		S1			=  08	; top of specifier queue		advance specifier queue by 1 entry
;751		S2			=  09,.VALIDITY=<A.S1>
;752						; second entry in specifier queue	advance specifier queue by 2 entries
;753		Q			=  0A	; shifter output latch
;754	;				=  0B	;					VA in A field
;755	;				=  0C	;					PSL in A, DST fields
;756	;				=  0D	;
;757		K.FFFF			=  0E	; Constant 0000FFFF (hex)
;758		RN.MODE.OPCODE		=  0F	; Rn (bits <31:28>)'CUR_MOD (bits <25:24>)'opcode (bits <23:16>)'
;759						; VAX Restart bit (bit<7>), 0 (bits <27:26,15:8,6:0>)
;760
;761		R0			=  10	; R0
;762		R1			=  11	; R1
;763		R2			=  12	; R2
;764		R3			=  13	; R3
;765		R4			=  14	; R4
;766		R5			=  15	; R5
;767		R6			=  16	; R6
;768		R7			=  17	; R7
;769		R8			=  18	; R8
;770		R9			=  19	; R9
;771		R10			=  1A	; R10
;772		R11			=  1B	; R11
;773		R12			=  1C	; R12
;774			AP		=  1C	;  argument pointer
;775		R13			=  1D	; R13
;776			FP		=  1D	;  frame pointer
;777		SP			=  1E	; R14 = stack pointer
;778	;				=  1F
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   29
;    DEFINE.MIC 	     Standard Microinstruction Format							      /REV=
;
;779
;780	;	Standard microinstruction format, continued.
;781
;782	;	This field controls whether the following are done as longwords or according to the
;783	;	prevailing data length:
;784	;		1. calculation of alu cc's
;785	;		2. zero extending of Wbus result
;786	;		3. size of memory operation
;787
;788	L/=<34>,.DEFAULT=<L/LONG>
;789
;790		LONG			=   0	; alu cc's, Wbus, memory operation are longword
;791		LEN(DL) 		=   1	; alu cc's, Wbus, memory operation are specified by DL
;792
;793	;	This field determines whether the ALU or the shifter drives the Wbus, and
;794	;	whether the ALU or shifter cc's are the input to the PSL condition code logic.
;795
;796	W/=<33>,.DEFAULT=<W/ALU>
;797
;798		ALU			=   0	; alu drives Wbus, alu cc's drive psl cc's
;799		SHF			=   1	; shifter drives Wbus, shifter cc's drive psl cc's
;800
;801	;	This field determines whether the VA register is updated from the ALU output.
;802
;803	V/=<32>,.DEFAULT=<V/HOLD.VA>
;804
;805		HOLD.VA 		=   0	; maintain current value of VA
;806		UPDATE.VA		=   1	; update VA from ALU output
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   30
;    DEFINE.MIC 	     Standard Microinstruction Format							      /REV=
;
;807
;808	;	Standard microinstruction format, continued.
;809
;810	;	This field defines the destination control.
;811
;812	;	The order and numbering of the values in the DST and A fields are identical.  If you change these values check
;813	;	the other field for a corresponding change.
;814
;815	DST/=<31:26>,.DEFAULT=<DST/WBUS>
;816
;817	;		Function	  Val		     Operation				    Comments
;818	;	-----------------------  ----	--------------------------------------- --------------------------------------------
;819		NONE			=  00	; No destination			No W-bus request is made
;820		W0			=  01	; working register 0
;821		W1			=  02	; working register 1
;822		W2			=  03	; working register 2
;823		W3			=  04	; working register 3
;824		W4			=  05	; working register 4
;825		W5			=  06	; working register 5
;826	;				=  07
;827
;828		WBUS			=  08	; W-bus 				Drive W-bus, S1 in A, B fields
;829		DST			=  09,.VALIDITY=<MRQ.NOP>
;830						; top of destination specifier queue	S2 in A, B field
;831	;				=  0A	;					Q in A, B fields
;832	;				=  0B	;					VA in A field
;833		PSL			=  0C	; PSL					writable as long only
;834		PSL.B0			=  0D	; PSL<7:0>				FBOX.FAULT.CODE in B field
;835	;				=  0E
;836	;				=  0F	;					RN.MODE.OPCODE in B field
;837
;838		R0			=  10	; R0
;839		R1			=  11	; R1
;840		R2			=  12	; R2
;841		R3			=  13	; R3
;842		R4			=  14	; R4
;843		R5			=  15	; R5
;844		R6			=  16	; R6
;845		R7			=  17	; R7
;846		R8			=  18	; R8
;847		R9			=  19	; R9
;848		R10			=  1A	; R10
;849		R11			=  1B	; R11
;850		R12			=  1C	; R12
;851			AP		=  1C	;  argument pointer
;852		R13			=  1D	; R13
;853			FP		=  1D	;  frame pointer
;854		SP			=  1E	; R14 = stack pointer
;855	;				=  1F	;
;856
;857		KSP			=  20	; kernel stack pointer
;858		ESP			=  21	; executive stack pointer
;859		SSP			=  22	; supervisor stack pointer
;860		USP			=  23	; user stack pointer
;861		ISP			=  24	; interrupt stack pointer
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   31
;    DEFINE.MIC 	     Standard Microinstruction Format							      /REV=
;
;862		ASTLVL			=  25	; ASTLVL value in bits <31:29>, machine check code in bits <23:16>,
;863						; CPUID in bits <7:0>
;864		SCBB			=  26	; system control block base register
;865		PCBB			=  27	; process control block base register
;866		SAVEPC			=  28	; console saved PC (also BPC after call to IE.CLEANUP.CPU)
;867		SAVEPSL 		=  29	; console saved PSL
;868	;				=  2A
;869	;				=  2B
;870	;				=  2C
;871	;				=  2D
;872	;				=  2E
;873	;				=  2F
;874
;875		INT.SYS 		=  30	; hw flops (bits <31:29,27,24>)'sisr<15:1> (bits<15:1>'iccs<6> (bit<0>)
;876	;				=  31	;					K0 in A field
;877	;				=  32	;					K1 in A field
;878	;				=  33	;
;879	;				=  34	;
;880		SC			=  35	; shift count
;881		MMGT.MODE		=  36	; mode for probing from <3:2>
;882	;				=  37	;					S+PSW_EX in A field
;883	;				=  38	;					POP.COUNT in A field
;884	;				=  39	;					SHIFT.SIGN in A field
;885		ECR			=  3A	; Ebox control register
;886	;				=  3B	;					PERF.COUNT in A field
;887		PCSCR			=  3C	; Patchable control store control register
;888	;				=  3D
;889	;				=  3E
;890	;				=  3F
;891	;				=  3F
;892	;				=  3F
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   32
;    DEFINE.MIC 	     Standard Microinstruction Format							      /REV=
;
;893
;894	;	Standard microinstruction format, continued.
;895
;896	;	This field defines the A port select.
;897
;898	;	The order and numbering of the values in the DST and A fields are identical.  If you change these values check
;899	;	the other field for a corresponding change.
;900
;901	A/=<25:20>,.DEFAULT=<A/NONE>
;902
;903	;		Function	  Val		     Operation				    Comments
;904	;	-----------------------  ----	--------------------------------------- --------------------------------------------
;905		NONE			=  00
;906		W0			=  01	; working register 0
;907		W1			=  02	; working register 1
;908		W2			=  03	; working register 2
;909		W3			=  04	; working register 3
;910		W4			=  05	; working register 4
;911		W5			=  06	; working register 5
;912	;				=  07
;913
;914		S1			=  08	; top of source specifier queue 	advance specifier queue by 1 entry
;915		S2			=  09,.VALIDITY=<B.S1>
;916						; top of destination specifier queue	advance specifier queue by 2 entries
;917		Q			=  0A	; shift result latch
;918		VA			=  0B	; virtual address register
;919		PSL			=  0C	; PSL register
;920	;				=  0D	;					FBOX.FAULT.CODE in B field
;921	;				=  0E
;922	;				=  0F
;923
;924		R0			=  10	; R0
;925		R1			=  11	; R1
;926		R2			=  12	; R2
;927		R3			=  13	; R3
;928		R4			=  14	; R4
;929		R5			=  15	; R5
;930		R6			=  16	; R6
;931		R7			=  17	; R7
;932		R8			=  18	; R8
;933		R9			=  19	; R9
;934		R10			=  1A	; R10
;935		R11			=  1B	; R11
;936		R12			=  1C	; R12
;937			AP		=  1C	;  argument pointer
;938		R13			=  1D	; R13
;939			FP		=  1D	;  frame pointer
;940		SP			=  1E	; R14 = stack pointer
;941	;				=  1F	;
;942
;943		KSP			=  20	; kernel stack pointer
;944		ESP			=  21	; executive stack pointer
;945		SSP			=  22	; supervisor stack pointer
;946		USP			=  23	; user stack pointer
;947		ISP			=  24	; interrupt stack pointer
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   33
;    DEFINE.MIC 	     Standard Microinstruction Format							      /REV=
;
;948		ASTLVL			=  25	; ASTLVL value in bits <31:29>, machine check code in bits <23:16>,
;949						; CPUID in bits <7:0>
;950		SCBB			=  26	; system control block base register
;951		PCBB			=  27	; process control block base register
;952		SAVEPC			=  28	; console saved PC
;953		SAVEPSL 		=  29	; console saved PSL
;954	;				=  2A
;955	;				=  2B
;956	;				=  2C
;957	;				=  2D
;958	;				=  2E
;959	;				=  2F
;960
;961		INT.SYS 		=  30	; 0 (bits<31:21>)'int.id (bits<20:16>)'sisr<15:1> (bits<15:1>'iccs<6> (bit<0>)
;962		K0			=  31	; constant 0
;963		K1			=  32	; constant 1
;964	;				=  33
;965	;				=  34
;966	;				=  35
;967	;				=  36
;968		S+PSW_EX		=  37	; opcode<0> in <29>'PSW<7:5> in <7:5>, else 0
;969		POP.COUNT		=  38	; mask bits set in mask processing unit
;970		SHIFT.SIGN		=  39	; shifter sign
;971		ECR			=  3A	; Ebox control register
;972		PERF.COUNT		=  3B	; Performance monitoring facility counters.  PMCTR0 in <31:16>,
;973						; PMCTR1 in <15:0>
;974		PCSCR			=  3C	; Patchable control store control register
;975	;				=  3D
;976	;				=  3E
;977	;				=  3F
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   34
;    DEFINE.MIC 	     Standard Microinstruction Format							      /REV=
;
;978
;979	;	Standard microinstruction format, continued.
;980
;981	;	This field is decoded to provide miscellaneous function control.
;982
;983	MISC/=<19:15>,.DEFAULT=<MISC/NOP>
;984
;985	;		Function	  Val		     Operation				    Comments
;986	;	-----------------------  ----	--------------------------------------- --------------------------------------------
;987		NOP			=  00	; no operation
;988		MULL			=  01	; Identifies an Fbox instruction as MULL
;989		CONST.10.BIT		=  02,.VALIDITY=<LIT.LIT>
;990						; Selects 10-bit B-bus constant from CONST.10 field
;991	;				=  03
;992		DL.BYTE 		=  04	; DL <-- byte				S3: change effects next microword
;993		DL.WORD 		=  05	; DL <-- word				S3: change effects next microword
;994		DL.LONG 		=  06	; DL <-- long				S3: change effects next microword
;995	;				=  07
;996		RESTART.IBOX		=  08	; restart I-box 			S5: prefetch and specifier processing
;997		RESTART.MBOX		=  09	; restart M-box 			S5: operand processing
;998	;				=  0A
;999	;				=  0B
;1000		RESET.CPU		=  0C	; reset I-box, M-box, F-box		S5: reset I-box and stop prefetch
;1001						;					S6: reset M-box and F-box,
;1002						;					    init register file valid bits
;1003	;				=  0D
;1004		CLR.PERF.COUNT		=  0E	; clear perf monitoring counters	S5: clear counters
;1005		INCR.PERF.COUNT 	=  0F	; increment perf monitoring counters	S5: increment counters
;1006
;1007		CLR.STATE.3-0		=  10	; clear flags<3:0>			S3: change effects next microword
;1008		SET.STATE.0		=  11	; set flag<0>				S3: change effects next microword
;1009		SET.STATE.1		=  12	; set flag<1>				S3: change effects next microword
;1010		SET.STATE.2		=  13	; set flag<2>				S3: change effects next microword
;1011		LOAD.SC.FROM.A		=  14	; SC <-- Abus
;1012		LOAD.MPU.FROM.B 	=  15	; MPU <-- Bbus<29:16>			S4: change effects microword+2
;1013	;				=  16
;1014	;				=  17
;1015		LOAD.PSL.CC.IIIP	=  18	; load PSL CCs with map IIIP		PSL.NZV  <--  WBUS.NZV
;1016						;					PSL.C	 <--  PSL.C (Unchanged)
;1017		LOAD.PSL.CC.JIZJ	=  19	; load PSL CCs with map JIZJ		PSL.N	 <--  WBUS.N XOR WBUS.V
;1018						;					PSL.Z	 <--  WBUS.Z
;1019						;					PSL.V	 <--  0
;1020						;					PSL.C	 <-- ~WBUS.C
;1021		LOAD.PSL.CC.IIII	=  1A	; load PSL CCs with map IIII		PSL.NZVC <--  WBUS.NZVC
;1022		LOAD.PSL.CC.IIIJ	=  1B	; load PSL CCs with map IIIJ		PSL.NZV  <--  WBUS.NZV
;1023						;					PSL.C	 <-- ~WBUS.C
;1024		LOAD.PSL.CC.IIIP.QUAD	= 1C	; load PSL CCs with map IIIP.quad	PSL.NV	 <--  WBUS.NV
;1025						;					PSL.Z	 <--  PSL.Z AND WBUS.Z
;1026						;					PSL.C	 <--  PSL.C (Unchanged)
;1027		LOAD.PSL.CC.PPJP	=  1D	; load PSL CCs with map PPJP		PSL.NZC  <--  PSL.NZC (unchanged)
;1028						;					PSL.V	 <--  not WBUS.Z
;1029			SIM.IE.INTEXC	=  1E	; IE.INTERRUPT/IE.EXCEPTION called	Simulator only; not in real hardware
;1030			SIM.HALT	=  1F	; stop simulator			Simulator only; not in real hardware
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   35
;    DEFINE.MIC 	     Special Microinstruction Format							      /REV=
;
;1031	.TOC	"	Special Microinstruction Format"
;1032
;1033	;	The fields for the special microinstruction are:
;1034	;
;1035	;	FORMAT/ 	SPECIAL
;1036	;	ALU/		ALU operation
;1037	;	MRQ/		Mbox request
;1038	;	MISC1/		Special miscellaneous 1
;1039	;	LIT/		B operand control, as follows:
;1040	;	    LIT/0:
;1041	;		MISC2/	Special miscellaneous 2
;1042	;		DISABLE.RETIRE/ Disable retire of instruction on LAST CYCLE
;1043	;		B/	B port select
;1044	;	    LIT/1:
;1045	;		POS/	Constant position	\ If MISC field does not
;1046	;		CONST/	8-bit constant value	/ contain CONST.10.BIT
;1047	;		CONST.10/ 10-bit constant value   If MISC field contains CONST.10.BIT
;1048	;	L/		Length control
;1049	;	W/		Wbus driver control
;1050	;	V/		VA latch update control
;1051	;	DST/		Wbus destination
;1052	;	A/		ALU A port select
;1053	;	MISC/		Miscellaneous
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   36
;    DEFINE.MIC 	     Special Microinstruction Format							      /REV=
;
;1054
;1055	;	Special microinstruction format, continued.
;1056
;1057	;	This field is the first miscellaneous function field.
;1058
;1059	MISC1/=<49:46>,.DEFAULT=<MISC1/NOP>
;1060
;1061	;		Function	  Val		     Operation				    Comments
;1062	;	-----------------------  ----	--------------------------------------- --------------------------------------------
;1063		NOP			=  00	; no operation
;1064		RETIRE.INSTRUCTION	=  01	; retire current instruction
;1065	;				=  02
;1066		FLUSH.VIC		=  03	; flush virtual instruction cache	S5: flush VIC.	REQUIRES A LOAD PC
;1067						;					BEFORE RESTARTING THE IBOX
;1068		FLUSH.BPC		=  04	; flush branch prediction table 	S5: flush branch prediction table
;1069		CLR.STATE.5-4		=  05	; state<5:4> <-- 0
;1070		SET.STATE.3		=  06	; state<3> <-- 1
;1071		SET.STATE.4		=  07	; state<4> <-- 1
;1072		SET.STATE.5		=  08	; state<5> <-- 1
;1073		FOP.VALID		=  09,.VALIDITY=<B.NOT.S1>
;1074						; F-box operand valid on FA/FB bus
;1075	;				=  09
;1076	;				=  0A
;1077	;				=  0B
;1078		FLUSH.PCQ		=  0C	; Flush Ibox PC queue
;1079	;				=  0D
;1080	;				=  0E
;1081	;				=  0F
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   37
;    DEFINE.MIC 	     Special Microinstruction Format							      /REV=
;
;1082
;1083	;	Special microinstruction format, continued.
;1084
;1085	;	This field is the second miscellaneous function field.
;1086
;1087	MISC2/=<44:41>,.DEFAULT=<MISC2/NOP>
;1088
;1089	;		Function	  Val		     Operation				    Comments
;1090	;	-----------------------  ----	--------------------------------------- --------------------------------------------
;1091		NOP			=  00	; no operation
;1092		F.DEST.CHECK		=  01	; Udate the Fbox scoreboard from the Dest list
;1093		FLUSH.PAQ		=  02,.VALIDITY=<MRQ.REQ>
;1094						; Flush Mbox PA queue			Must be done with MRQ field request
;1095	;				=  03
;1096	;				=  04
;1097	;				=  05
;1098	;				=  06
;1099	;				=  07
;1100	;				=  08
;1101	;				=  09
;1102	;				=  0A
;1103	;				=  0B
;1104	;				=  0C
;1105	;				=  0D
;1106	;				=  0E
;1107	;				=  0F
;1108
;1109
;1110	;	This bit disables the retire of an instruction when LAST.CYCLE
;1111	;	is decoded from the SEQ.MUX field.
;1112
;1113	DISABLE.RETIRE/=<40>,.DEFAULT=<DISABLE.RETIRE/NO>
;1114
;1115	;		Function	  Val		     Operation				    Comments
;1116	;	-----------------------  ----	--------------------------------------- --------------------------------------------
;1117		NO			=  0	; Do not diable retire of instruction (the normal thing)
;1118		YES			=  1	; Disable retire of instruction
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   38
;    DEFINE.MIC 	     Microsequencer Control Fields							      /REV=
;
;1119	.TOC	"	Microsequencer Control Fields"
;1120
;1121	;	The microsequencer control fields supply the information necessary for the microsequencer
;1122	;	to calculate the address of the next microinstruction.	The basic computation done by
;1123	;	the microsequencer involves selecting a base address from one of several sources, and then
;1124	;	optionally modifying 3 bits of the base address to get the final next address.
;1125
;1126	;	This field defines the format of the microsequencer control fields.  The microsequencer uses
;1127	;	this bit to block the latch which contains bits <10:8> of the next address.  This means that
;1128	;	the destination of a BRANCH format microinstruction must be in the same 256-location page
;1129	;	as the branch itself.
;1130
;1131	SEQ.FMT/=<14>,.DEFAULT=<SEQ.FMT/JUMP>
;1132
;1133		JUMP			=   0	; format is JUMP
;1134		BRANCH			=   1	; format is BRANCH
;1135
;1136	;	This field controls whether the current micro-PC is pushed on the microsubroutine stack.
;1137
;1138	SEQ.CALL/=<13>,.DEFAULT=<SEQ.CALL/NOP>
;1139
;1140		NOP			=   0	; don't call subroutine
;1141		CALL			=   1	; call subroutine
;1142
;1143	;	For the jump format, this field controls the next-address selection via the NA mux.
;1144
;1145	SEQ.MUX/=<12:11>,.DEFAULT=<SEQ.MUX/J>
;1146
;1147	;		Select		  Val		  Address Source				    Comments
;1148	;	-----------------------  ----	--------------------------------------- --------------------------------------------
;1149		J			=   0	; current microword			uword<10:0>
;1150		STACK			=   1	; microstack				pops top entry from microstack
;1151		LAST.CYCLE		=   2	; I-box 				new microflow
;1152		LAST.CYCLE.OVERFLOW	=   3	; I-box 				new microflow, enable int overflow trap
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   39
;    DEFINE.MIC 	     Microsequencer Control Fields							      /REV=
;
;1153
;1154	;	Microsequencer control fields, continued.
;1155
;1156	;	This field defines the microbranch condition used to modify base address bits <3:1> in a BRANCH format
;1157	;	microinstruction.  In the real microword format, this field occupies the bits specified by the SEQ.COND field.
;1158	;	In the fake microword format, this field is placed in the SEQ.COND.1 field so that a full 11-bit next-address
;1159	;	can be specified in all microwords, including BRANCH format microinstructions.	The SEQ.COND.1 field is moved
;1160	;	to the SEQ.COND field by the allocator to construct the final microword format.
;1161
;1162	SEQ.COND.1/=<65:61>,.DEFAULT=<SEQ.COND.1/0> ; 'Fake' microbranch condition
;1163
;1164	SEQ.COND/=<12:8>			; 'Real' microbranch condition
;1165
;1166	;	Note: AMUX tests on sign values (bits<31>, <15>, <7>) should affect the same NA bit.
;1167
;1168	;	       Select		  Val	Modifier bits for NA<3:1>			Comments
;1169	;	-----------------------  ----	--------------------------------------- --------------------------------------------
;1170		NOP			=  00	; No microbranch condition
;1171		ALU.NZV 		=  01	; alu<n>'alu<z>'alu<v>			set by microinstruction .-2
;1172		ALU.NZC 		=  02	; alu<n>'alu<z>'alu<c>			set by microinstruction .-2
;1173		B.2-0			=  03	; Bbus<2:0>				set by microinstruction .-1
;1174		B.5-3			=  04	; Bbus<5:3>				set by microinstruction .-1
;1175		A.7-5			=  05	; Abus<7:5>				set by microinstruction .-1
;1176		A.15-12 		=  06	; Abus<15>'Abus<14>'(Abus<13> OR Abus<12>) set by microinstruction .-1
;1177		A31.BQA.BNZ1		=  07	; Abus<31>'Bbus<2:0> = 0'(Bbus<15:8> NE 0) set by microinstruction .-1
;1178		MPU.0-6 		=  08	; mask proc unit output 		loaded by microinstruction .-2
;1179		MPU.7-13		=  09	; mask proc unit output 		loaded by microinstruction .-2
;1180		STATE.2-0		=  0A	; state<2:0>				set by microinstruction .-1
;1181		STATE.5-3		=  0B	; state<5:3>				set by microinstruction .-1
;1182		OPCODE.2-0		=  0C	; opcode<2:0>
;1183		PSL.26-24		=  0D	; PSL<26:24>
;1184		PSL.29.23-22		=  0E	; PSL<29,23:22>
;1185		SHF.NZ.INT		=  0F	; shf<n>'shf<z>'interrupt		set by microinstruction .-2
;1186
;1187		TEST.PINS		=  10	; vector present'test data'test strobe
;1188			VECTOR		=  10	; vector present'test data'test strobe
;1189		FBOX.CONDITION		=  11	; Priority encoded Fbox fault code<1:0>'Fbox disabled
;1190		FQ.VR			=  12	; 0'field queue not valid'field queue rmode
;1191						; 000 = valid,memory / 001 = valid,register
;1192						; 010 (not used)     / 011 = queue not valid
;1193	;				13..1F
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   40
;    DEFINE.MIC 	     Microsequencer Control Fields							      /REV=
;
;1194
;1195	;	Microsequencer control fields, continued.
;1196
;1197	;	This field gives the address of the next microinstruction if the current microinstruction is JUMP format.
;1198
;1199	J/=<10:0>,.NEXTADDRESS
;1200
;1201	;	This field gives the 8-bit page offset of the next microinstruction if the current microinstruction is BRANCH
;1202	;	format.  The remaining 3 bits of the 11-bit address are taken from the corresponding bits of the current microPC.
;1203	;	This field is never used by MICRO2.  The allocator selectively fills it in based on the format of the
;1204	;	microinstruction.
;1205
;1206	BR.OFF/=<7:0>
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   41
;    DEFINE.MIC 	     Simulation and Assembly Control Fields						      /REV=
;
;1207	.TOC	"	Simulation and Assembly Control Fields"
;1208
;1209	;	The following field definitions are used to provide necessary information to the performance model.
;1210	;	They are removed from the microword by the allocator when the microcode is built for the behavioral
;1211	;	model or the actual chip.  They are retained by the allocator when the microcode is built for the
;1212	;	performance model.
;1213
;1214	;	This field selects which field contains performance model commands.
;1215	;
;1216	;	NOTE: PEBOX.PAS HAS INTIMATE KNOWLEDGE OF THESE DEFINITIONS.
;1217
;1218	SIM.CTRL/=<78>,.DEFAULT=<SIM.CTRL/NONE>
;1219
;1220		CMD			=  0	; Command in the SIM.ADDR field (CMD.xxx)
;1221		NONE			=  1	; No performance model command
;1222	;
;1223	;	When the SIM.CTRL field contains CMD, the following overlapping field contains the command.
;1224	;	This field overlaps with the SIM.COND field.  Therefore if the SIM.CTRL field selects CMD then
;1225	;	the SIM.COND and SIM.COND.SEL fields do not contain valid values.
;1226	;
;1227	SIM.CMD/=<68:66>
;1228	;
;1229	;	      Command		 Val			   Interpretation
;1230	;	----------------------	 ---	---------------------------------------------------
;1231		SIM.ERROR		= 00	; Illegal microword
;1232		EXCEPTION		= 01	; Microcode exception handler reached
;1233		RSVD.OPCODE		= 02	; Reserved opcode handler reached
;1234		EMULATE 		= 03	; Emulated instruction handler reached
;1235		VECTOR.FAULT		= 04	; Vector fault handler reached
;1236	;				= 05	;
;1237	;				= 06	;
;1238	;				= 07	;
;1239	;				= 08	;
;1240	;				= 09	;
;1241	;				= 0A	;
;1242	;				= 0B	;
;1243	;				= 0C	;
;1244	;				= 0D	;
;1245	;				= 0E	;
;1246	;				= 0F	;
;1247
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   42
;    DEFINE.MIC 	     Simulation and Assembly Control Fields						      /REV=
;
;1248
;1249	;	Simulation and assembly control fields, continued.
;1250
;1251	;	This field determines if the SIM.ADDR field alone contains the address source or if that value
;1252	;	is offset +/- a constant.
;1253	;
;1254	;	NOTE: PEBOX.PAS HAS INTIMATE KNOWLEDGE OF THESE DEFINITIONS.
;1255
;1256	SIM.ADDR.SEL/=<77>,.DEFAULT=<SIM.ADDR.SEL/ADDR.K>
;1257
;1258		ADDR			=  0	; Compute address from SIM.ADDR
;1259		ADDR.K			=  1	; Compute address from SIM.ADDR +/- constant
;1260
;1261	;	This field selects the address source for a memory reference.  It does not contain a valid address source
;1262	;	if the field contains NONE, or if the SIM.CTRL field contains CMD (in the latter case, this field
;1263	;	contains a simulator command instead).
;1264
;1265	SIM.ADDR/=<76:72>,.DEFAULT=<SIM.ADDR/NONE>
;1266
;1267	;	   Address Select	 Val			   Interpretation
;1268	;	----------------------	 ---	---------------------------------------------------
;1269		NONE			= 00	; No valid adress
;1270
;1271		K			= 01	; Constant from microword
;1272		EA.1			= 02	; Address of first operand specifier
;1273		EA.2			= 03	; Address of second operand specifier
;1274		EA.3			= 04	; Address of third operand specifier
;1275		SP			= 05	; Stack pointer
;1276		SP.2			= 06	; Second stack pointer value in trace
;1277		SP.EXTENT		= 07	; Farthest stack extent for CALLx, RET, PUSHR, POPR
;1278		CASE			= 08	; Address of CASE displacement
;1279		FIELD			= 09	; Aligned address of bit field
;1280		QUEUE.1 		= 0A	; First queue reference
;1281		QUEUE.2 		= 0B	; Second queue instruction
;1282		QUEUE.HDR		= 0C	; Queue header address
;1283		PCB			= 0D	; Process control block base address
;1284		SCB			= 0E	; System control block base address
;1285		PROBE			= 0F	; Probe extent address
;1286
;1287	;				= 10	;
;1288	;				= 11	;
;1289	;				= 12	;
;1290	;				= 13	;
;1291	;				= 14	;
;1292	;				= 15	;
;1293	;				= 16	;
;1294	;				= 17	;
;1295	;				= 18	;
;1296	;				= 19	;
;1297	;				= 1A	;
;1298	;				= 1B	;
;1299	;				= 1C	;
;1300	;				= 1D	;
;1301	;				= 1E	;
;1302	;				= 1F	;
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   43
;    DEFINE.MIC 	     Simulation and Assembly Control Fields						      /REV=
;
;1303
;1304	;	Simulation and assembly control fields, continued.
;1305
;1306	;	This field selects the microbranch recipe to be used to generate the next microword address for
;1307	;	a conditional branch instruction.  This field only has a valid value if the SIM.COND.SEL field
;1308	;	contains SIM.COND.FNC and the SIM.CTRL field selects NONE.
;1309	;
;1310	;	NOTE: PEBOX.PAS HAS INTIMATE KNOWLEDGE OF THESE DEFINITIONS.
;1311
;1312	SIM.COND/=<70:66>,.DEFAULT=<SIM.COND/NONE>
;1313
;1314	;	   Condition Select	 Val	     General Use		S3 condition		       S4 condition
;1315	;	-----------------------  ---	----------------------- ------------------------------- -------------------------------
;1316		NONE			= 00	; None			None				None
;1317
;1318		S3.V.PS 		= 01	; Vfield		pos<=31'size=0'size<=32 	None
;1319		S3.V.A			= 02	; Vfield		0'0'pos+size<32 		None
;1320		S3.SV			= 03	; ASHx			shift count<7:5>		None
;1321		S3.CALLX		= 04	; CALLx 		mask<15>'mask<14>'0		None
;1322		S3.ACBX 		= 05	; ACBx			Operand sign'0'0		None
;1323		S34.MASK14		= 06	; PUSHR/POPR		0'mask<14>'0			0'mask<14:0>=0'0
;1324		S34.IPR 		= 07	; MxPR			0'0'0				0'1'0
;1325		S34.QUEUE		= 08	; Queue conditions	0'1'0				0'0'0
;1326		S34.000 		= 09	; Miscellaneous 	0'0'0				0'0'0
;1327		S4.QUEUE.EMPTY		= 0A	; Queue instructions	None				0'PSL<V>=1'0
;1328		S4.QUEUE.SINGLE 	= 0B	; Queue instructions	None				0'queue_addr [2]=0'0
;1329		S4.CHAR.MATCH		= 0C	; STRING		None				0'character match'0'
;1330		S4.CASEX		= 0D	; CASEx 		None				0'0'case out of range
;1331	;				= 0E	;
;1332	;				= 0F	;
;1333
;1334	;				= 10	;
;1335	;				= 11	;
;1336	;				= 12	;
;1337	;				= 13	;
;1338	;				= 14	;
;1339	;				= 15	;
;1340	;				= 16	;
;1341	;				= 17	;
;1342	;				= 18	;
;1343	;				= 19	;
;1344	;				= 1A	;
;1345	;				= 1B	;
;1346	;				= 1C	;
;1347	;				= 1D	;
;1348	;				= 1E	;
;1349	;				= 1F	;
;1350	;
;1351	;	This field is used to select whether the condition is a constant or a function defined by the SIM.COND field.
;1352	;	If the condtion is a constant, the value is in the overlapping field SIM.COND.K.
;1353	;	This field does not contain a valid value if the SIM.CTRL field selects CMD.
;1354
;1355	SIM.COND.SEL/=<71>,.DEFAULT=<SIM.COND.SEL/FNC>
;1356
;1357		FNC			=  0	; Condition in SIM.COND field
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   44
;    DEFINE.MIC 	     Simulation and Assembly Control Fields						      /REV=
;
;1358		CONST			=  1	; S3/S4 constant condition in SIM.COND.K
;1359
;1360	;	This overlapping field determines which E-box pipe segment the constant simulation condition is for.
;1361	;	The value of this bit is unpredictable if the SIM.COND.SEL field is selecting SIM.COND.FNC.
;1362
;1363	SIM.COND.S3.S4/=<70>
;1364		S3			= 0	; constant condition is for S3
;1365		S4			= 1	; constant condition is for S4
;1366
;1367	;	This overlapping field is used to supply a 3-bit constant when the SIM.COND.SEL field contains SIM.COND.K
;1368
;1369	SIM.COND.K/=<68:66>
;1370
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   45
;    DEFINE.MIC 	     Validity Checks									      /REV=
;
;1371	.TOC	"	Validity Checks"
;1372
;1373
;1374	;	A field must contain reference to S1.
;1375	.SET/A.S1=<.EQL[<A/>,<A/S1>]>
;1376
;1377	;	B field must contain reference to S1.
;1378	.SET/B.S1=<.EQL[<B/>,<B/S1>]>
;1379
;1380	;	B field must not contain reference to S1
;1381	.SET/B.NOT.S1=<.NEQ[<B/>,<B/S1>]>
;1382
;1383	;	SEQ.MUX field must contain LAST CYCLE or LAST CYCLE OVERFLOW.
;1384	.SET/MUX.LAST=<.OR[<.EQL[<SEQ.MUX/>,<SEQ.MUX/LAST.CYCLE>]>,
;1385			   <.EQL[<SEQ.MUX/>,<SEQ.MUX/LAST.CYCLE.OVERFLOW>]>]>
;1386
;1387	;	MRQ field must contain effective NOP
;1388	.SET/MRQ.NOP=<.OR[<.EQL[<MRQ/>,<MRQ/NOP>]>,
;1389			  <.EQL[<MRQ/>,<MRQ/SYNC.BDISP>]>,
;1390			  <.EQL[<MRQ/>,<MRQ/SYNC.BDISP.RETIRE>]>,
;1391			  <.EQL[<MRQ/>,<MRQ/SYNC.BDISP.TEST.PRED>]>]>
;1392
;1393	;	MRQ field must not contain effective NOP
;1394	.SET/MRQ.REQ=<.AND[<.NEQ[<MRQ/>,<MRQ/NOP>]>,
;1395			   <.NEQ[<MRQ/>,<MRQ/SYNC.BDISP>]>,
;1396			   <.NEQ[<MRQ/>,<MRQ/SYNC.BDISP.RETIRE>]>,
;1397			   <.NEQ[<MRQ/>,<MRQ/SYNC.BDISP.TEST.PRED>]>]>
;1398
;1399	;	LIT field must contain LIT decode
;1400	.SET/LIT.LIT=<.EQL[<LIT/>,<LIT/LIT>]>
;1401
;1402	;	DST field must contain a working register
;1403	.SET/DST.WN=<.AND[<.GEQ[<DST/>,<DST/W0>]>,<.LEQ[<DST/>,<DST/W5>]>]>
;1404
;1405	;	DST field must contain a GPR
;1406	.SET/DST.RN=<.AND[<.GEQ[<DST/>,<DST/R0>]>,<.LEQ[<DST/>,<DST/SP>]>]>
;1407
;1408	;	DST field must contain a working register or a GPR
;1409	.SET/DST.WN.OR.RN=<.OR[<DST.WN>,<DST.RN>]>
;1410
;1411	.cref
				;1412	.bin
				;1413	.ecode
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   46
;     MACRO.MIC 	     MACRO.MIC -- Macro Definitions							      /REV=
;
				;1414	.TOC	"MACRO.MIC -- Macro Definitions"
				;1415	.TOC	"Revision 1.1"
				;1416
				;1417	;	Bob Supnik
				;1418
;1419	.nobin
;1420	;****************************************************************************
;1421	;*									    *
;1422	;*  COPYRIGHT (c) 1987, 1988, 1989, 1990, 1991, 1992 BY 		    *
;1423	;*  DIGITAL EQUIPMENT CORPORATION, MAYNARD, MASSACHUSETTS.		    *
;1424	;*  ALL RIGHTS RESERVED.						    *
;1425	;*									    *
;1426	;*  THIS SOFTWARE IS FURNISHED UNDER A LICENSE AND MAY BE USED AND COPIED   *
;1427	;*  ONLY IN  ACCORDANCE WITH  THE  TERMS  OF  SUCH  LICENSE  AND WITH THE   *
;1428	;*  INCLUSION OF THE ABOVE COPYRIGHT NOTICE.  THIS SOFTWARE OR ANY  OTHER   *
;1429	;*  COPIES THEREOF MAY NOT BE PROVIDED OR OTHERWISE MADE AVAILABLE TO ANY   *
;1430	;*  OTHER PERSON.  NO TITLE TO AND OWNERSHIP OF  THE  SOFTWARE IS  HEREBY   *
;1431	;*  TRANSFERRED.							    *
;1432	;*									    *
;1433	;*  THE INFORMATION IN THIS SOFTWARE IS  SUBJECT TO CHANGE WITHOUT NOTICE   *
;1434	;*  AND  SHOULD  NOT  BE  CONSTRUED AS	A COMMITMENT BY DIGITAL EQUIPMENT   *
;1435	;*  CORPORATION.							    *
;1436	;*									    *
;1437	;*  DIGITAL ASSUMES NO RESPONSIBILITY FOR THE USE  OR  RELIABILITY OF ITS   *
;1438	;*  SOFTWARE ON EQUIPMENT WHICH IS NOT SUPPLIED BY DIGITAL.		    *
;1439	;*									    *
;1440	;****************************************************************************
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   47
;     MACRO.MIC 	     Revision History									      /REV=
;
;1441	.TOC	"	Revision History"
;1442
;1443	; Edit	  Date	 Who	     Description
;1444	; ---- --------- ---	---------------------
;1445	;    1 20-May-91 GMU	Symptom: No macro to invoke a console halt with
;1446	;				 no cleanup.
;1447	;			Cure:	 Add CONSOLE HALT NO CLEANUP []
;1448	; (1)0 17-Jul-90 GMU	Initial production microcode.
;1449	;
;1450	; Begin version 1.0 here
;1451	;   25 04-Jul-90 GMU	Add performance monitoring facility macros.
;1452	;   24 01-May-90 GMU	Change position of machine check code field in MACHINE CHECK
;1453	;			macro.
;1454	;   23 23-Feb-90 GMU	Add new macros for MxPr rewrite.
;1455	;   22 20-Feb-90 GMU	Remove macros that reference unused decodes.
;1456	;   21 12-Feb-90 GMU	Add sim ie.intexc macro.
;1457	;   20 19-JAN-90 GMU	FLUSH BRANCH PREDICTION CACHE -> FLUSH BRANCH PREDICTION TABLE.
;1458	;   19 12-Dec-89 GMU	Remove SYNC FBOX macro.
;1459	;   18 07-Dec-89 GMU	Move soon-to-be-obsolted macros to the end for easy
;1460	;			removal later.
;1461	;   17 06-Dec-89 GMU	Rename FLUSH BPC to FLUSH BRANCH PREDICTION CACHE.
;1462	;   16 30-Nov-89 GMU	Add [] - [] - 1 macro, remove ALU macros that use
;1463	;			PSL<C> carry-in.
;1464	;   15 17-Nov-89 GMU	Remove obsolete macros.
;1465	;   14 08-Nov-89 GMU	Remove edit 13.
;1466	;   13 04-Nov-89 GMU	Clear state<3:0> in CONSOLE HALT MACRO.
;1467	;   12 19-Oct-89 DGM	Add NODST macros for all ALU operations
;1468	;   11 18-OCT-89 GMU	Add PCB read/write macros.
;1469	;   10 28-Sep-89 GMU	Add new probe macro.
;1470	;    9 21-Sep-89 GMU	Add new macros.
;1471	;    8 20-Sep-89 GMU	Add macros for MRQ/TB.TAG.FILL and MRQ/TB.PTE.FILL.
;1472	;    7 11-Sep-89 GMU	Add .MODE to PROBE macros to emphasize mode is from register.
;1473	;    6 15-Aug-89 GMU	Turn CLEAR WRITE BUFFERS macro into MRQ/NOP for now.
;1474	;    5	2-Aug-89 DGM	Modified SMUL and UDIV macros to update Q
;1475	;    4 12-Jul-89 GMU	Added definitions to support CPU init on exception.
;1476	;    3 30-Jun-89 DGM	Added macros: SMUL ; NODST <-- PASSx ; MULL
;1477	;    2 28-Jun-89 GMU	Corrected error in retire branch queue macro.
;1478	;    1 22-Nov-88 DB	Add FBOX DEST CHECK
;1479	; (0)0 14-Sep-87 RMS	Trial microcode.
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   48
;     MACRO.MIC 	     ALU Macros 									      /REV=
;
;1480	.TOC	"	ALU Macros"
;1481
;1482	;	ALU macros with register operands that drive the Wbus.
;1483
;1484	[] <-- [] + []			"LIT/BREG,ALU/A.PLUS.B,DST/@1,A/@2,B/@3,W/ALU"
;1485	[] <-- [] + [] + 1		"LIT/BREG,ALU/A.PLUS.B.PLUS.1,DST/@1,A/@2,B/@3,W/ALU"
;1486	[] <-- [] - []			"LIT/BREG,ALU/A.MINUS.B,DST/@1,A/@2,B/@3,W/ALU"
;1487	[] <-- [] - [] - 1		"LIT/BREG,ALU/A.MINUS.B.MINUS.1,DST/@1,A/@2,B/@3,W/ALU"
;1488	[] <-- [] AND []		"LIT/BREG,ALU/A.AND.B,DST/@1,A/@2,B/@3,W/ALU"
;1489	[] <-- NOT [] AND []		"LIT/BREG,ALU/NOT.A.AND.B,DST/@1,A/@2,B/@3,W/ALU"
;1490	[] <-- [] ANDNOT []		"LIT/BREG,ALU/A.AND.NOT.B,DST/@1,A/@2,B/@3,W/ALU"
;1491	[] <-- [] OR [] 		"LIT/BREG,ALU/A.OR.B,DST/@1,A/@2,B/@3,W/ALU"
;1492	[] <-- [] XOR []		"LIT/BREG,ALU/A.XOR.B,DST/@1,A/@2,B/@3,W/ALU"
;1493	[] <-- (-[] + [])		"LIT/BREG,ALU/B.MINUS.A,DST/@1,A/@2,B/@3,W/ALU"
;1494	[] <-- [] UDIV []		"FORMAT/STANDARD,LIT/BREG,ALU/UDIV.STEP,SHF/NOP,DST/@1,A/@2,B/@3,W/ALU,Q/UPDATE.Q"
;1495	[] <-- [] SMUL []		"FORMAT/STANDARD,LIT/BREG,ALU/SMUL.STEP,SHF/NOP,DST/@1,A/@2,B/@3,W/ALU,Q/UPDATE.Q"
;1496
;1497	[] <-- []			"ALU/PASS.A,DST/@1,A/@2,W/ALU"
;1498	[] <-- [] + 1			"ALU/A.PLUS.1,DST/@1,A/@2,W/ALU"
;1499	[] <-- [] - 1			"ALU/A.MINUS.1,DST/@1,A/@2,W/ALU"
;1500	[] <-- [] + 4			"ALU/A.PLUS.4,DST/@1,A/@2,W/ALU"
;1501	[] <-- [] - 4			"ALU/A.MINUS.4,DST/@1,A/@2,W/ALU"
;1502	[] <-- -[]			"LIT/BREG,ALU/NEG.B,DST/@1,B/@2,W/ALU"
;1503	[] <-- NOT []			"LIT/BREG,ALU/NOT.B,DST/@1,B/@2,W/ALU"
;1504	[] <-- B []			"LIT/BREG,ALU/PASS.B,DST/@1,B/@2,W/ALU"
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   49
;     MACRO.MIC 	     ALU Macros 									      /REV=
;
;1505
;1506	;	ALU macros, continued.
;1507
;1508	;	ALU macros with register operands that drive VA.
;1509
;1510	VA <-- [] + []			"LIT/BREG,ALU/A.PLUS.B,A/@1,B/@2,V/UPDATE.VA"
;1511	VA <-- [] + [] + 1		"LIT/BREG,ALU/A.PLUS.B.PLUS.1,A/@1,B/@2,V/UPDATE.VA"
;1512	VA <-- [] - []			"LIT/BREG,ALU/A.MINUS.B,A/@1,B/@2,V/UPDATE.VA"
;1513	VA <-- [] AND []		"LIT/BREG,ALU/A.AND.B,A/@1,B/@2,V/UPDATE.VA"
;1514	VA <-- NOT [] AND []		"LIT/BREG,ALU/NOT.A.AND.B,A/@1,B/@2,V/UPDATE.VA"
;1515	VA <-- [] ANDNOT []		"LIT/BREG,ALU/A.AND.NOT.B,A/@1,B/@2,V/UPDATE.VA"
;1516	VA <-- [] OR [] 		"LIT/BREG,ALU/A.OR.B,A/@1,B/@2,V/UPDATE.VA"
;1517	VA <-- [] XOR []		"LIT/BREG,ALU/A.XOR.B,A/@1,B/@2,V/UPDATE.VA"
;1518	VA <-- (-[] + [])		"LIT/BREG,ALU/B.MINUS.A,A/@1,B/@2,V/UPDATE.VA"
;1519
;1520	VA <-- []			"ALU/PASS.A,A/@1,V/UPDATE.VA"
;1521	VA <-- [] + 1			"ALU/A.PLUS.1,A/@1,V/UPDATE.VA"
;1522	VA <-- [] - 1			"ALU/A.MINUS.1,A/@1,V/UPDATE.VA"
;1523	VA <-- [] + 4			"ALU/A.PLUS.4,A/@1,V/UPDATE.VA"
;1524	VA <-- [] - 4			"ALU/A.MINUS.4,A/@1,V/UPDATE.VA"
;1525	VA <-- -[]			"LIT/BREG,ALU/NEG.B,B/@1,V/UPDATE.VA"
;1526	VA <-- NOT []			"LIT/BREG,ALU/NOT.B,B/@1,V/UPDATE.VA"
;1527	VA <-- B []			"LIT/BREG,ALU/PASS.B,B/@1,V/UPDATE.VA"
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   50
;     MACRO.MIC 	     ALU Macros 									      /REV=
;
;1528
;1529	;	ALU macros, continued.
;1530
;1531	;	ALU macros with constant operand that drive the Wbus.
;1532
;1533	[] <-- [] + K10.[]		"LIT/LIT,MISC/CONST.10.BIT,ALU/A.PLUS.B,CONST.10/@3,DST/@1,A/@2,W/ALU"
;1534	[] <-- [] - K10.[]		"LIT/LIT,MISC/CONST.10.BIT,ALU/A.MINUS.B,CONST.10/@3,DST/@1,A/@2,W/ALU"
;1535	[] <-- K10.[] - []		"LIT/LIT,MISC/CONST.10.BIT,ALU/B.MINUS.A,CONST.10/@2,DST/@1,A/@3,W/ALU"
;1536	[] <-- [] AND K10.[]		"LIT/LIT,MISC/CONST.10.BIT,ALU/A.AND.B,CONST.10/@3,DST/@1,A/@2,W/ALU"
;1537	[] <-- [] OR K10.[]		"LIT/LIT,MISC/CONST.10.BIT,ALU/A.OR.B,CONST.10/@3,DST/@1,A/@2,W/ALU"
;1538	[] <-- [] ANDNOT K10.[] 	"LIT/LIT,MISC/CONST.10.BIT,ALU/A.AND.NOT.B,CONST.10/@3,DST/@1,A/@2,W/ALU"
;1539	[] <-- [] XOR K10.[]		"LIT/LIT,MISC/CONST.10.BIT,ALU/A.XOR.B,CONST.10/@3,DST/@1,A/@2,W/ALU"
;1540	[] <-- NOT K10.[]		"LIT/LIT,MISC/CONST.10.BIT,ALU/NOT.B,CONST.10/@2,DST/@1,W/ALU"
;1541	[] <-- -K10.[]			"LIT/LIT,MISC/CONST.10.BIT,ALU/NEG.B,CONST.10/@2,DST/@1,W/ALU"
;1542	[] <-- K10.[]			"LIT/LIT,MISC/CONST.10.BIT,ALU/PASS.B,CONST.10/@2,DST/@1,W/ALU"
;1543
;1544	[] <-- [] + 000000[]		"LIT/LIT,POS/BYTE0,ALU/A.PLUS.B,CONST/@3,DST/@1,A/@2,W/ALU"
;1545	[] <-- [] - 000000[]		"LIT/LIT,POS/BYTE0,ALU/A.MINUS.B,CONST/@3,DST/@1,A/@2,W/ALU"
;1546	[] <-- 000000[] - []		"LIT/LIT,POS/BYTE0,ALU/B.MINUS.A,CONST/@2,DST/@1,A/@3,W/ALU"
;1547	[] <-- [] AND 000000[]		"LIT/LIT,POS/BYTE0,ALU/A.AND.B,CONST/@3,DST/@1,A/@2,W/ALU"
;1548	[] <-- [] OR 000000[]		"LIT/LIT,POS/BYTE0,ALU/A.OR.B,CONST/@3,DST/@1,A/@2,W/ALU"
;1549	[] <-- [] ANDNOT 000000[]	"LIT/LIT,POS/BYTE0,ALU/A.AND.NOT.B,CONST/@3,DST/@1,A/@2,W/ALU"
;1550	[] <-- [] XOR 000000[]		"LIT/LIT,POS/BYTE0,ALU/A.XOR.B,CONST/@3,DST/@1,A/@2,W/ALU"
;1551	[] <-- NOT 000000[]		"LIT/LIT,POS/BYTE0,ALU/NOT.B,CONST/@2,DST/@1,W/ALU"
;1552	[] <-- -000000[]		"LIT/LIT,POS/BYTE0,ALU/NEG.B,CONST/@2,DST/@1,W/ALU"
;1553	[] <-- 000000[] 		"LIT/LIT,POS/BYTE0,ALU/PASS.B,CONST/@2,DST/@1,W/ALU"
;1554
;1555	[] <-- [] + 0000[]00		"LIT/LIT,POS/BYTE1,ALU/A.PLUS.B,CONST/@3,DST/@1,A/@2,W/ALU"
;1556	[] <-- [] - 0000[]00		"LIT/LIT,POS/BYTE1,ALU/A.MINUS.B,CONST/@3,DST/@1,A/@2,W/ALU"
;1557	[] <-- 0000[]00 - []		"LIT/LIT,POS/BYTE1,ALU/B.MINUS.A,CONST/@2,DST/@1,A/@3,W/ALU"
;1558	[] <-- [] AND 0000[]00		"LIT/LIT,POS/BYTE1,ALU/A.AND.B,CONST/@3,DST/@1,A/@2,W/ALU"
;1559	[] <-- [] OR 0000[]00		"LIT/LIT,POS/BYTE1,ALU/A.OR.B,CONST/@3,DST/@1,A/@2,W/ALU"
;1560	[] <-- [] ANDNOT 0000[]00	"LIT/LIT,POS/BYTE1,ALU/A.AND.NOT.B,CONST/@3,DST/@1,A/@2,W/ALU"
;1561	[] <-- [] XOR 0000[]00		"LIT/LIT,POS/BYTE1,ALU/A.XOR.B,CONST/@3,DST/@1,A/@2,W/ALU"
;1562	[] <-- NOT 0000[]00		"LIT/LIT,POS/BYTE1,ALU/NOT.B,CONST/@2,DST/@1,W/ALU"
;1563	[] <-- -0000[]00		"LIT/LIT,POS/BYTE1,ALU/NEG.B,CONST/@2,DST/@1,W/ALU"
;1564	[] <-- 0000[]00 		"LIT/LIT,POS/BYTE1,ALU/PASS.B,CONST/@2,DST/@1,W/ALU"
;1565
;1566	[] <-- [] + 00[]0000		"LIT/LIT,POS/BYTE2,ALU/A.PLUS.B,CONST/@3,DST/@1,A/@2,W/ALU"
;1567	[] <-- [] - 00[]0000		"LIT/LIT,POS/BYTE2,ALU/A.MINUS.B,CONST/@3,DST/@1,A/@2,W/ALU"
;1568	[] <-- 00[]0000 - []		"LIT/LIT,POS/BYTE2,ALU/B.MINUS.A,CONST/@2,DST/@1,A/@3,W/ALU"
;1569	[] <-- [] AND 00[]0000		"LIT/LIT,POS/BYTE2,ALU/A.AND.B,CONST/@3,DST/@1,A/@2,W/ALU"
;1570	[] <-- [] OR 00[]0000		"LIT/LIT,POS/BYTE2,ALU/A.OR.B,CONST/@3,DST/@1,A/@2,W/ALU"
;1571	[] <-- [] ANDNOT 00[]0000	"LIT/LIT,POS/BYTE2,ALU/A.AND.NOT.B,CONST/@3,DST/@1,A/@2,W/ALU"
;1572	[] <-- [] XOR 00[]0000		"LIT/LIT,POS/BYTE2,ALU/A.XOR.B,CONST/@3,DST/@1,A/@2,W/ALU"
;1573	[] <-- NOT 00[]0000		"LIT/LIT,POS/BYTE2,ALU/NOT.B,CONST/@2,DST/@1,W/ALU"
;1574	[] <-- -00[]0000		"LIT/LIT,POS/BYTE2,ALU/NEG.B,CONST/@2,DST/@1,W/ALU"
;1575	[] <-- 00[]0000 		"LIT/LIT,POS/BYTE2,ALU/PASS.B,CONST/@2,DST/@1,W/ALU"
;1576
;1577	[] <-- [] + []000000		"LIT/LIT,POS/BYTE3,ALU/A.PLUS.B,CONST/@3,DST/@1,A/@2,W/ALU"
;1578	[] <-- [] - []000000		"LIT/LIT,POS/BYTE3,ALU/A.MINUS.B,CONST/@3,DST/@1,A/@2,W/ALU"
;1579	[] <-- []000000 - []		"LIT/LIT,POS/BYTE3,ALU/B.MINUS.A,CONST/@2,DST/@1,A/@3,W/ALU"
;1580	[] <-- [] AND []000000		"LIT/LIT,POS/BYTE3,ALU/A.AND.B,CONST/@3,DST/@1,A/@2,W/ALU"
;1581	[] <-- [] OR []000000		"LIT/LIT,POS/BYTE3,ALU/A.OR.B,CONST/@3,DST/@1,A/@2,W/ALU"
;1582	[] <-- [] ANDNOT []000000	"LIT/LIT,POS/BYTE3,ALU/A.AND.NOT.B,CONST/@3,DST/@1,A/@2,W/ALU"
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   51
;     MACRO.MIC 	     ALU Macros 									      /REV=
;
;1583	[] <-- [] XOR []000000		"LIT/LIT,POS/BYTE3,ALU/A.XOR.B,CONST/@3,DST/@1,A/@2,W/ALU"
;1584	[] <-- NOT []000000		"LIT/LIT,POS/BYTE3,ALU/NOT.B,CONST/@2,DST/@1,W/ALU"
;1585	[] <-- -[]000000		"LIT/LIT,POS/BYTE3,ALU/NEG.B,CONST/@2,DST/@1,W/ALU"
;1586	[] <-- []000000 		"LIT/LIT,POS/BYTE3,ALU/PASS.B,CONST/@2,DST/@1,W/ALU"
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   52
;     MACRO.MIC 	     ALU Macros 									      /REV=
;
;1587
;1588	;	ALU macros, continued.
;1589
;1590	;	ALU macros with constant operand that drive VA.
;1591
;1592	VA <-- [] + K10.[]		"LIT/LIT,MISC/CONST.10.BIT,ALU/A.PLUS.B,CONST.10/@2,A/@1,V/UPDATE.VA"
;1593	VA <-- [] - K10.[]		"LIT/LIT,MISC/CONST.10.BIT,ALU/A.MINUS.B,CONST.10/@2,A/@1,V/UPDATE.VA"
;1594	VA <-- K10.[] - []		"LIT/LIT,MISC/CONST.10.BIT,ALU/B.MINUS.A,CONST.10/@1,A/@2,V/UPDATE.VA"
;1595	VA <-- [] AND K10.[]		"LIT/LIT,MISC/CONST.10.BIT,ALU/A.AND.B,CONST.10/@2,A/@1,V/UPDATE.VA"
;1596	VA <-- [] OR K10.[]		"LIT/LIT,MISC/CONST.10.BIT,ALU/A.OR.B,CONST.10/@2,A/@1,V/UPDATE.VA"
;1597	VA <-- [] ANDNOT K10.[] 	"LIT/LIT,MISC/CONST.10.BIT,ALU/A.AND.NOT.B,CONST.10/@2,A/@1,V/UPDATE.VA"
;1598	VA <-- [] XOR K10.[]		"LIT/LIT,MISC/CONST.10.BIT,ALU/A.XOR.B,CONST.10/@2,A/@1,V/UPDATE.VA"
;1599	VA <-- NOT K10.[]		"LIT/LIT,MISC/CONST.10.BIT,ALU/NOT.B,CONST.10/@1,V/UPDATE.VA"
;1600	VA <-- -K10.[]			"LIT/LIT,MISC/CONST.10.BIT,ALU/NEG.B,CONST.10/@1,V/UPDATE.VA"
;1601	VA <-- K10.[]			"LIT/LIT,MISC/CONST.10.BIT,ALU/PASS.B,CONST.10/@1,V/UPDATE.VA"
;1602
;1603	VA <-- [] + 000000[]		"LIT/LIT,POS/BYTE0,ALU/A.PLUS.B,CONST/@2,A/@1,V/UPDATE.VA"
;1604	VA <-- [] - 000000[]		"LIT/LIT,POS/BYTE0,ALU/A.MINUS.B,CONST/@2,A/@1,V/UPDATE.VA"
;1605	VA <-- 000000[] - []		"LIT/LIT,POS/BYTE0,ALU/B.MINUS.A,CONST/@1,A/@2,V/UPDATE.VA"
;1606	VA <-- [] AND 000000[]		"LIT/LIT,POS/BYTE0,ALU/A.AND.B,CONST/@2,A/@1,V/UPDATE.VA"
;1607	VA <-- [] OR 000000[]		"LIT/LIT,POS/BYTE0,ALU/A.OR.B,CONST/@2,A/@1,V/UPDATE.VA"
;1608	VA <-- [] ANDNOT 000000[]	"LIT/LIT,POS/BYTE0,ALU/A.AND.NOT.B,CONST/@2,A/@1,V/UPDATE.VA"
;1609	VA <-- [] XOR 000000[]		"LIT/LIT,POS/BYTE0,ALU/A.XOR.B,CONST/@2,A/@1,V/UPDATE.VA"
;1610	VA <-- NOT 000000[]		"LIT/LIT,POS/BYTE0,ALU/NOT.B,CONST/@1,V/UPDATE.VA"
;1611	VA <-- -000000[]		"LIT/LIT,POS/BYTE0,ALU/NEG.B,CONST/@1,V/UPDATE.VA"
;1612	VA <-- 000000[] 		"LIT/LIT,POS/BYTE0,ALU/PASS.B,CONST/@1,V/UPDATE.VA"
;1613
;1614	VA <-- [] + 0000[]00		"LIT/LIT,POS/BYTE1,ALU/A.PLUS.B,CONST/@2,A/@1,V/UPDATE.VA"
;1615	VA <-- [] - 0000[]00		"LIT/LIT,POS/BYTE1,ALU/A.MINUS.B,CONST/@2,A/@1,V/UPDATE.VA"
;1616	VA <-- 0000[]00 - []		"LIT/LIT,POS/BYTE1,ALU/B.MINUS.A,CONST/@1,A/@2,V/UPDATE.VA"
;1617	VA <-- [] AND 0000[]00		"LIT/LIT,POS/BYTE1,ALU/A.AND.B,CONST/@2,A/@1,V/UPDATE.VA"
;1618	VA <-- [] OR 0000[]00		"LIT/LIT,POS/BYTE1,ALU/A.OR.B,CONST/@2,A/@1,V/UPDATE.VA"
;1619	VA <-- [] ANDNOT 0000[]00	"LIT/LIT,POS/BYTE1,ALU/A.AND.NOT.B,CONST/@2,A/@1,V/UPDATE.VA"
;1620	VA <-- [] XOR 0000[]00		"LIT/LIT,POS/BYTE1,ALU/A.XOR.B,CONST/@2,A/@1,V/UPDATE.VA"
;1621	VA <-- NOT 0000[]00		"LIT/LIT,POS/BYTE1,ALU/NOT.B,CONST/@1,V/UPDATE.VA"
;1622	VA <-- -0000[]00		"LIT/LIT,POS/BYTE1,ALU/NEG.B,CONST/@1,V/UPDATE.VA"
;1623	VA <-- 0000[]00 		"LIT/LIT,POS/BYTE1,ALU/PASS.B,CONST/@1,V/UPDATE.VA"
;1624
;1625	VA <-- [] + 00[]0000		"LIT/LIT,POS/BYTE2,ALU/A.PLUS.B,CONST/@2,A/@1,V/UPDATE.VA"
;1626	VA <-- [] - 00[]0000		"LIT/LIT,POS/BYTE2,ALU/A.MINUS.B,CONST/@2,A/@1,V/UPDATE.VA"
;1627	VA <-- 00[]0000 - []		"LIT/LIT,POS/BYTE2,ALU/B.MINUS.A,CONST/@1,A/@2,V/UPDATE.VA"
;1628	VA <-- [] AND 00[]0000		"LIT/LIT,POS/BYTE2,ALU/A.AND.B,CONST/@2,A/@1,V/UPDATE.VA"
;1629	VA <-- [] OR 00[]0000		"LIT/LIT,POS/BYTE2,ALU/A.OR.B,CONST/@2,A/@1,V/UPDATE.VA"
;1630	VA <-- [] ANDNOT 00[]0000	"LIT/LIT,POS/BYTE2,ALU/A.AND.NOT.B,CONST/@2,A/@1,V/UPDATE.VA"
;1631	VA <-- [] XOR 00[]0000		"LIT/LIT,POS/BYTE2,ALU/A.XOR.B,CONST/@2,A/@1,V/UPDATE.VA"
;1632	VA <-- NOT 00[]0000		"LIT/LIT,POS/BYTE2,ALU/NOT.B,CONST/@1,V/UPDATE.VA"
;1633	VA <-- -00[]0000		"LIT/LIT,POS/BYTE2,ALU/NEG.B,CONST/@1,V/UPDATE.VA"
;1634	VA <-- 00[]0000 		"LIT/LIT,POS/BYTE2,ALU/PASS.B,CONST/@1,V/UPDATE.VA"
;1635
;1636	VA <-- [] + []000000		"LIT/LIT,POS/BYTE3,ALU/A.PLUS.B,CONST/@2,A/@1,V/UPDATE.VA"
;1637	VA <-- [] - []000000		"LIT/LIT,POS/BYTE3,ALU/A.MINUS.B,CONST/@2,A/@1,V/UPDATE.VA"
;1638	VA <-- []000000 - []		"LIT/LIT,POS/BYTE3,ALU/B.MINUS.A,CONST/@1,A/@2,V/UPDATE.VA"
;1639	VA <-- [] AND []000000		"LIT/LIT,POS/BYTE3,ALU/A.AND.B,CONST/@2,A/@1,V/UPDATE.VA"
;1640	VA <-- [] OR []000000		"LIT/LIT,POS/BYTE3,ALU/A.OR.B,CONST/@2,A/@1,V/UPDATE.VA"
;1641	VA <-- [] ANDNOT []000000	"LIT/LIT,POS/BYTE3,ALU/A.AND.NOT.B,CONST/@2,A/@1,V/UPDATE.VA"
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   53
;     MACRO.MIC 	     ALU Macros 									      /REV=
;
;1642	VA <-- [] XOR []000000		"LIT/LIT,POS/BYTE3,ALU/A.XOR.B,CONST/@2,A/@1,V/UPDATE.VA"
;1643	VA <-- NOT []000000		"LIT/LIT,POS/BYTE3,ALU/NOT.B,CONST/@1,V/UPDATE.VA"
;1644	VA <-- -[]000000		"LIT/LIT,POS/BYTE3,ALU/NEG.B,CONST/@1,V/UPDATE.VA"
;1645	VA <-- []000000 		"LIT/LIT,POS/BYTE3,ALU/PASS.B,CONST/@1,V/UPDATE.VA"
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   54
;     MACRO.MIC 	     ALU Macros 									      /REV=
;
;1646
;1647	;	ALU macros, continued.
;1648
;1649	;	ALU macros with register operands that have no destination.
;1650
;1651	NODST <-- [] + []		"LIT/BREG,ALU/A.PLUS.B,A/@1,B/@2"
;1652	NODST <-- [] + [] + 1		"LIT/BREG,ALU/A.PLUS.B.PLUS.1,A/@1,B/@2"
;1653	NODST <-- [] - []		"LIT/BREG,ALU/A.MINUS.B,A/@1,B/@2"
;1654	NODST <-- [] AND []		"LIT/BREG,ALU/A.AND.B,A/@1,B/@2"
;1655	NODST <-- NOT [] AND [] 	"LIT/BREG,ALU/NOT.A.AND.B,A/@1,B/@2"
;1656	NODST <-- [] ANDNOT []		"LIT/BREG,ALU/A.AND.NOT.B,A/@1,B/@2"
;1657	NODST <-- [] OR []		"LIT/BREG,ALU/A.OR.B,A/@1,B/@2"
;1658	NODST <-- [] XOR []		"LIT/BREG,ALU/A.XOR.B,A/@1,B/@2"
;1659	NODST <-- (-[] + [])		"LIT/BREG,ALU/B.MINUS.A,A/@1,B/@2"
;1660
;1661	NODST <-- []			"ALU/PASS.A,A/@1"
;1662	NODST <-- [] + 1		"ALU/A.PLUS.1,A/@1"
;1663	NODST <-- [] - 1		"ALU/A.MINUS.1,A/@1"
;1664	NODST <-- [] + 4		"ALU/A.PLUS.4,A/@1"
;1665	NODST <-- [] - 4		"ALU/A.MINUS.4,A/@1"
;1666	NODST <-- -[]			"LIT/BREG,ALU/NEG.B,B/@1"
;1667	NODST <-- NOT []		"LIT/BREG,ALU/NOT.B,B/@1"
;1668	NODST <-- B []			"LIT/BREG,ALU/PASS.B,B/@1"
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   55
;     MACRO.MIC 	     ALU Macros 									      /REV=
;
;1669
;1670	;	ALU macros, continued.
;1671
;1672	;	ALU macros with constant operand that have no destination.
;1673
;1674	NODST <-- [] + K10.[]		"LIT/LIT,MISC/CONST.10.BIT,ALU/A.PLUS.B,CONST.10/@2,A/@1"
;1675	NODST <-- [] - K10.[]		"LIT/LIT,MISC/CONST.10.BIT,ALU/A.MINUS.B,CONST.10/@2,A/@1"
;1676	NODST <-- K10.[] - []		"LIT/LIT,MISC/CONST.10.BIT,ALU/B.MINUS.A,CONST.10/@1,A/@2"
;1677	NODST <-- [] AND K10.[] 	"LIT/LIT,MISC/CONST.10.BIT,ALU/A.AND.B,CONST.10/@2,A/@1"
;1678	NODST <-- [] OR K10.[]		"LIT/LIT,MISC/CONST.10.BIT,ALU/A.OR.B,CONST.10/@2,A/@1"
;1679	NODST <-- [] ANDNOT K10.[]	"LIT/LIT,MISC/CONST.10.BIT,ALU/A.AND.NOT.B,CONST.10/@2,A/@1"
;1680	NODST <-- [] XOR K10.[] 	"LIT/LIT,MISC/CONST.10.BIT,ALU/A.XOR.B,CONST.10/@2,A/@1"
;1681	NODST <-- NOT K10.[]		"LIT/LIT,MISC/CONST.10.BIT,ALU/NOT.B,CONST.10/@1"
;1682	NODST <-- -K10.[]		"LIT/LIT,MISC/CONST.10.BIT,ALU/NEG.B,CONST.10/@1"
;1683	NODST <-- K10.[]		"LIT/LIT,MISC/CONST.10.BIT,ALU/PASS.B,CONST.10/@1"
;1684
;1685	NODST <-- [] + 000000[] 	"LIT/LIT,POS/BYTE0,ALU/A.PLUS.B,CONST/@2,A/@1"
;1686	NODST <-- [] - 000000[] 	"LIT/LIT,POS/BYTE0,ALU/A.MINUS.B,CONST/@2,A/@1"
;1687	NODST <-- 000000[] - [] 	"LIT/LIT,POS/BYTE0,ALU/B.MINUS.A,CONST/@1,A/@2"
;1688	NODST <-- [] AND 000000[]	"LIT/LIT,POS/BYTE0,ALU/A.AND.B,CONST/@2,A/@1"
;1689	NODST <-- [] OR 000000[]	"LIT/LIT,POS/BYTE0,ALU/A.OR.B,CONST/@2,A/@1"
;1690	NODST <-- [] ANDNOT 000000[]	"LIT/LIT,POS/BYTE0,ALU/A.AND.NOT.B,CONST/@2,A/@1"
;1691	NODST <-- [] XOR 000000[]	"LIT/LIT,POS/BYTE0,ALU/A.XOR.B,CONST/@2,A/@1"
;1692	NODST <-- NOT 000000[]		"LIT/LIT,POS/BYTE0,ALU/NOT.B,CONST/@1"
;1693	NODST <-- -000000[]		"LIT/LIT,POS/BYTE0,ALU/NEG.B,CONST/@1"
;1694	NODST <-- 000000[]		"LIT/LIT,POS/BYTE0,ALU/PASS.B,CONST/@1"
;1695
;1696	NODST <-- [] + 0000[]00 	"LIT/LIT,POS/BYTE1,ALU/A.PLUS.B,CONST/@2,A/@1"
;1697	NODST <-- [] - 0000[]00 	"LIT/LIT,POS/BYTE1,ALU/A.MINUS.B,CONST/@2,A/@1"
;1698	NODST <-- 0000[]00 - [] 	"LIT/LIT,POS/BYTE1,ALU/B.MINUS.A,CONST/@1,A/@2"
;1699	NODST <-- [] AND 0000[]00	"LIT/LIT,POS/BYTE1,ALU/A.AND.B,CONST/@2,A/@1"
;1700	NODST <-- [] OR 0000[]00	"LIT/LIT,POS/BYTE1,ALU/A.OR.B,CONST/@2,A/@1"
;1701	NODST <-- [] ANDNOT 0000[]00	"LIT/LIT,POS/BYTE1,ALU/A.AND.NOT.B,CONST/@2,A/@1"
;1702	NODST <-- [] XOR 0000[]00	"LIT/LIT,POS/BYTE1,ALU/A.XOR.B,CONST/@2,A/@1"
;1703	NODST <-- NOT 0000[]00		"LIT/LIT,POS/BYTE1,ALU/NOT.B,CONST/@1"
;1704	NODST <-- -0000[]00		"LIT/LIT,POS/BYTE1,ALU/NEG.B,CONST/@1"
;1705	NODST <-- 0000[]00		"LIT/LIT,POS/BYTE1,ALU/PASS.B,CONST/@1"
;1706
;1707	NODST <-- [] + 00[]0000 	"LIT/LIT,POS/BYTE2,ALU/A.PLUS.B,CONST/@2,A/@1"
;1708	NODST <-- [] - 00[]0000 	"LIT/LIT,POS/BYTE2,ALU/A.MINUS.B,CONST/@2,A/@1"
;1709	NODST <-- 00[]0000 - [] 	"LIT/LIT,POS/BYTE2,ALU/B.MINUS.A,CONST/@1,A/@2"
;1710	NODST <-- [] AND 00[]0000	"LIT/LIT,POS/BYTE2,ALU/A.AND.B,CONST/@2,A/@1"
;1711	NODST <-- [] OR 00[]0000	"LIT/LIT,POS/BYTE2,ALU/A.OR.B,CONST/@2,A/@1"
;1712	NODST <-- [] ANDNOT 00[]0000	"LIT/LIT,POS/BYTE2,ALU/A.AND.NOT.B,CONST/@2,A/@1"
;1713	NODST <-- [] XOR 00[]0000	"LIT/LIT,POS/BYTE2,ALU/A.XOR.B,CONST/@2,A/@1"
;1714	NODST <-- NOT 00[]0000		"LIT/LIT,POS/BYTE2,ALU/NOT.B,CONST/@1"
;1715	NODST <-- -00[]0000		"LIT/LIT,POS/BYTE2,ALU/NEG.B,CONST/@1"
;1716	NODST <-- 00[]0000		"LIT/LIT,POS/BYTE2,ALU/PASS.B,CONST/@1"
;1717
;1718	NODST <-- [] + []000000 	"LIT/LIT,POS/BYTE3,ALU/A.PLUS.B,CONST/@2,A/@1"
;1719	NODST <-- [] - []000000 	"LIT/LIT,POS/BYTE3,ALU/A.MINUS.B,CONST/@2,A/@1"
;1720	NODST <-- []000000 - [] 	"LIT/LIT,POS/BYTE3,ALU/B.MINUS.A,CONST/@1,A/@2"
;1721	NODST <-- [] AND []000000	"LIT/LIT,POS/BYTE3,ALU/A.AND.B,CONST/@2,A/@1"
;1722	NODST <-- [] OR []000000	"LIT/LIT,POS/BYTE3,ALU/A.OR.B,CONST/@2,A/@1"
;1723	NODST <-- [] ANDNOT []000000	"LIT/LIT,POS/BYTE3,ALU/A.AND.NOT.B,CONST/@2,A/@1"
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   56
;     MACRO.MIC 	     ALU Macros 									      /REV=
;
;1724	NODST <-- [] XOR []000000	"LIT/LIT,POS/BYTE3,ALU/A.XOR.B,CONST/@2,A/@1"
;1725	NODST <-- NOT []000000		"LIT/LIT,POS/BYTE3,ALU/NOT.B,CONST/@1"
;1726	NODST <-- -[]000000		"LIT/LIT,POS/BYTE3,ALU/NEG.B,CONST/@1"
;1727	NODST <-- []000000		"LIT/LIT,POS/BYTE3,ALU/PASS.B,CONST/@1"
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   57
;     MACRO.MIC 	     ALU Macros 									      /REV=
;
;1728
;1729	;	ALU macros, continued.
;1730
;1731	;	Special ALU macros.
;1732
;1733	NOP				"[WBUS] <-- [NONE],LONG"
;1734	NOP NODEST			"[NONE] <-- [NONE],LONG"
;1735	SET PSL(V)			"[WBUS] <-- 000000[01],LONG,SET PSL CC.PPJP"
;1736	CLEAR PSL(V)			"[WBUS] <-- 000000[00],LONG,SET PSL CC.PPJP"
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   58
;     MACRO.MIC 	     MEMREQ Macros									      /REV=
;
;1737	.TOC	"	MEMREQ Macros"
;1738
;1739	[] <-- MEM (VA) 		"MRQ/READ.V.RCHK,DST/@1"
;1740	[] <-- MEM.PR (VA)		"MRQ/READ.PR,DST/@1"
;1741	[] <-- MEM.LOCK (VA)		"MRQ/READ.V.LOCK,DST/@1"
;1742	[] <-- MEM.SCB (VA)		"MRQ/READ.P,DST/@1"
;1743	[] <-- MEM.PCB (VA)		"MRQ/READ.P,DST/@1"
;1744	[] <-- MEM.PHYS (VA)		"MRQ/READ.P,DST/@1"
;1745	[] <-- MEM.WCHK (VA)		"MRQ/READ.V.WCHK,DST/@1"
;1746	[] <-- MEM.NOCHK (VA)		"MRQ/READ.V.NOCHK,DST/@1"
;1747	[] <-- PROBE.R.MODE (VA)	"MRQ/PROBE.V.RCHK,DST/@1"
;1748	[] <-- PROBE.W.MODE (VA)	"MRQ/PROBE.V.WCHK,DST/@1"
;1749	[] <-- PROBE.R.MODE.NOFILL (VA) "MRQ/PROBE.V.RCHK.NOFILL,DST/@1"
;1750
;1751	MEM (VA)&			"MRQ/WRITE.V.WCHK"
;1752	MEM.PR (VA)&			"MRQ/WRITE.PR"
;1753	MEM.UNLOCK (VA)&		"MRQ/WRITE.V.UNLOCK"
;1754	MEM.NOCHK (VA)& 		"MRQ/WRITE.V.NOCHK"
;1755	MEM.PHYS (VA)&			"MRQ/WRITE.P"
;1756	MEM.PCB (VA)&			"MRQ/WRITE.P"
;1757	WCHK (VA)&			"MRQ/WCHK"
;1758
;1759	SYNCHRONIZE MBOX		"MRQ/SYNC.MBOX"
;1760	TB INVALIDATE SINGLE		"MRQ/TB.INVALIDATE.SINGLE"
;1761	TB INVALIDATE PROCESS		"MRQ/TB.INVALIDATE.PROCESS"
;1762	TB INVALIDATE ALL		"MRQ/TB.INVALIDATE.ALL"
;1763	TB TAG FILL			"MRQ/TB.TAG.FILL"
;1764	TB PTE FILL			"MRQ/TB.PTE.FILL"
;1765	LOAD PC 			"MRQ/LOAD.PC"
;1766
;1767	WAIT BDISP VALID		"MRQ/SYNC.BDISP"
;1768	RETIRE UNCOND BQ ENTRY		"MRQ/SYNC.BDISP.RETIRE"
;1769	RETIRE COND BQ ENTRY		"MRQ/SYNC.BDISP.TEST.PRED"
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   59
;     MACRO.MIC 	     SHIFT Macros									      /REV=
;
;1770	.TOC	"	SHIFT Macros"
;1771
;1772	;	Shift macros with register operands that drive the Wbus.
;1773
;1774	[] <-- [] LROT []		"FORMAT/STANDARD,LIT/BREG,VAL/@3,DST/@1,B/@2,A/@2,SHF/LEFT.DOUBLE,W/SHF"
;1775	[] <-- [] LROT (SC)		"FORMAT/STANDARD,LIT/BREG,VAL/0,DST/@1,B/@2,A/@2,SHF/LEFT.DOUBLE,W/SHF"
;1776	[] <-- [] RROT []		"FORMAT/STANDARD,LIT/BREG,VAL/@3,DST/@1,B/@2,A/@2,SHF/RIGHT.DOUBLE,W/SHF"
;1777	[] <-- [] RROT (SC)		"FORMAT/STANDARD,LIT/BREG,VAL/0,DST/@1,B/@2,A/@2,SHF/RIGHT.DOUBLE,W/SHF"
;1778	[] <-- [] RROT (32-SC)		"FORMAT/STANDARD,LIT/BREG,VAL/0,DST/@1,B/@2,A/@2,SHF/LEFT.DOUBLE,W/SHF"
;1779	[] <-- []!![] LSH []		"FORMAT/STANDARD,LIT/BREG,VAL/@4,DST/@1,B/@3,A/@2,SHF/LEFT.DOUBLE,W/SHF"
;1780	[] <-- []!![] LSH (SC)		"FORMAT/STANDARD,LIT/BREG,VAL/0,DST/@1,B/@3,A/@2,SHF/LEFT.DOUBLE,W/SHF"
;1781	[] <-- []!![] RSH []		"FORMAT/STANDARD,LIT/BREG,VAL/@4,DST/@1,B/@3,A/@2,SHF/RIGHT.DOUBLE,W/SHF"
;1782	[] <-- []!![] RSH (SC)		"FORMAT/STANDARD,LIT/BREG,VAL/0,DST/@1,B/@3,A/@2,SHF/RIGHT.DOUBLE,W/SHF"
;1783	[] <-- []!![] RSH (32-SC)	"FORMAT/STANDARD,LIT/BREG,VAL/0,DST/@1,B/@3,A/@2,SHF/LEFT.DOUBLE,W/SHF"
;1784	[] <-- SEXT [] RSH []		"FORMAT/STANDARD,LIT/BREG,VAL/@3,DST/@1,B/@2,A/SHIFT.SIGN,SHF/RIGHT.DOUBLE,W/SHF"
;1785	[] <-- SEXT [] RSH (SC) 	"FORMAT/STANDARD,LIT/BREG,VAL/0,DST/@1,B/@2,A/SHIFT.SIGN,SHF/RIGHT.DOUBLE,W/SHF"
;1786	[] <-- SEXT [] RSH (32-SC)	"FORMAT/STANDARD,LIT/BREG,VAL/0,DST/@1,B/@2,A/SHIFT.SIGN,SHF/LEFT.DOUBLE,W/SHF"
;1787
;1788	[] <-- PASSA [] 		"FORMAT/STANDARD,DST/@1,A/@2,SHF/PASS.A,W/SHF"
;1789	[] <-- PASSB [] 		"FORMAT/STANDARD,LIT/BREG,DST/@1,B/@2,SHF/PASS.B,W/SHF"
;1790	[] <-- 0			"FORMAT/STANDARD,DST/@1,SHF/PASS.Z,W/SHF"
;1791	[] <-- [] LSH []		"FORMAT/STANDARD,LIT/BREG,VAL/@3,DST/@1,A/@2,SHF/LEFT.SINGLE,W/SHF"
;1792	[] <-- [] LSH (SC)		"FORMAT/STANDARD,LIT/BREG,VAL/0,DST/@1,A/@2,SHF/LEFT.SINGLE,W/SHF"
;1793	[] <-- ZEXT [] RSH []		"FORMAT/STANDARD,LIT/BREG,VAL/@3,DST/@1,B/@2,SHF/RIGHT.SINGLE,W/SHF"
;1794	[] <-- ZEXT [] RSH (SC) 	"FORMAT/STANDARD,LIT/BREG,VAL/0,DST/@1,B/@2,SHF/RIGHT.SINGLE,W/SHF"
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   60
;     MACRO.MIC 	     SHIFT Macros									      /REV=
;
;1795
;1796	;	Shift macros, continued.
;1797
;1798	;	Shift macros with register operands that drive the shift latch.
;1799
;1800	Q <-- [] LROT []		"FORMAT/STANDARD,LIT/BREG,VAL/@2,B/@1,A/@1,SHF/LEFT.DOUBLE,Q/UPDATE.Q"
;1801	Q <-- [] LROT (SC)		"FORMAT/STANDARD,LIT/BREG,VAL/0,B/@1,A/@1,SHF/LEFT.DOUBLE,Q/UPDATE.Q"
;1802	Q <-- [] RROT []		"FORMAT/STANDARD,LIT/BREG,VAL/@2,B/@1,A/@1,SHF/RIGHT.DOUBLE,Q/UPDATE.Q"
;1803	Q <-- [] RROT (SC)		"FORMAT/STANDARD,LIT/BREG,VAL/0,B/@1,A/@1,SHF/RIGHT.DOUBLE,Q/UPDATE.Q"
;1804	Q <-- []!![] LSH []		"FORMAT/STANDARD,LIT/BREG,VAL/@3,B/@2,A/@1,SHF/LEFT.DOUBLE,Q/UPDATE.Q"
;1805	Q <-- []!![] LSH (SC)		"FORMAT/STANDARD,LIT/BREG,VAL/0,B/@2,A/@1,SHF/LEFT.DOUBLE,Q/UPDATE.Q"
;1806	Q <-- []!![] RSH []		"FORMAT/STANDARD,LIT/BREG,VAL/@3,B/@2,A/@1,SHF/RIGHT.DOUBLE,Q/UPDATE.Q"
;1807	Q <-- []!![] RSH (SC)		"FORMAT/STANDARD,LIT/BREG,VAL/0,B/@2,A/@1,SHF/RIGHT.DOUBLE,Q/UPDATE.Q"
;1808	Q <-- []!![] RSH (32-SC)	"FORMAT/STANDARD,LIT/BREG,VAL/0,B/@2,A/@1,SHF/LEFT.DOUBLE,Q/UPDATE.Q"
;1809	Q <-- SEXT [] RSH []		"FORMAT/STANDARD,LIT/BREG,VAL/@2,B/@1,A/SHIFT.SIGN,SHF/RIGHT.DOUBLE,Q/UPDATE.Q"
;1810	Q <-- SEXT [] RSH (SC)		"FORMAT/STANDARD,LIT/BREG,VAL/0,B/@1,A/SHIFT.SIGN,SHF/RIGHT.DOUBLE,Q/UPDATE.Q"
;1811	Q <-- SEXT [] RSH (32-SC)	"FORMAT/STANDARD,LIT/BREG,VAL/0,B/@1,A/SHIFT.SIGN,SHF/LEFT.DOUBLE,Q/UPDATE.Q"
;1812
;1813	Q <-- PASSA []			"FORMAT/STANDARD,A/@1,SHF/PASS.A,Q/UPDATE.Q"
;1814	Q <-- PASSB []			"FORMAT/STANDARD,LIT/BREG,B/@1,SHF/PASS.B,Q/UPDATE.Q"
;1815	Q <-- 0 			"FORMAT/STANDARD,SHF/PASS.Z,Q/UPDATE.Q"
;1816	Q <-- [] LSH [] 		"FORMAT/STANDARD,LIT/BREG,VAL/@2,A/@1,SHF/LEFT.SINGLE,Q/UPDATE.Q"
;1817	Q <-- [] LSH (SC)		"FORMAT/STANDARD,LIT/BREG,VAL/0,A/@1,SHF/LEFT.SINGLE,Q/UPDATE.Q"
;1818	Q <-- ZEXT [] RSH []		"FORMAT/STANDARD,LIT/BREG,VAL/@2,B/@1,SHF/RIGHT.SINGLE,Q/UPDATE.Q"
;1819	Q <-- ZEXT [] RSH (SC)		"FORMAT/STANDARD,LIT/BREG,VAL/0,B/@1,SHF/RIGHT.SINGLE,Q/UPDATE.Q"
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   61
;     MACRO.MIC 	     SHIFT Macros									      /REV=
;
;1820
;1821	;	Shift macros, continued.
;1822
;1823	;	Shift macros with constant operand that drive the Wbus.
;1824
;1825	[] <-- PASSB K10.[]		"FORMAT/STANDARD,LIT/LIT,MISC/CONST.10.BIT,DST/@1,CONST.10/@2,SHF/PASS.B,W/SHF"
;1826	[] <-- PASSB 000000[]		"FORMAT/STANDARD,LIT/LIT,POS/BYTE0,DST/@1,CONST/@2,SHF/PASS.B,W/SHF"
;1827	[] <-- PASSB 0000[]00		"FORMAT/STANDARD,LIT/LIT,POS/BYTE1,DST/@1,CONST/@2,SHF/PASS.B,W/SHF"
;1828	[] <-- PASSB 00[]0000		"FORMAT/STANDARD,LIT/LIT,POS/BYTE2,DST/@1,CONST/@2,SHF/PASS.B,W/SHF"
;1829	[] <-- PASSB []000000		"FORMAT/STANDARD,LIT/LIT,POS/BYTE3,DST/@1,CONST/@2,SHF/PASS.B,W/SHF"
;1830
;1831	;	Shift macros with constant operand that drive the shift latch.
;1832
;1833	Q <-- PASSB K10.[]		"FORMAT/STANDARD,LIT/LIT,MISC/CONST.10.BIT,CONST.10/@1,SHF/PASS.B,Q/UPDATE.Q"
;1834	Q <-- PASSB 000000[]		"FORMAT/STANDARD,LIT/LIT,POS/BYTE0,CONST/@1,SHF/PASS.B,Q/UPDATE.Q"
;1835	Q <-- PASSB 0000[]00		"FORMAT/STANDARD,LIT/LIT,POS/BYTE1,CONST/@1,SHF/PASS.B,Q/UPDATE.Q"
;1836	Q <-- PASSB 00[]0000		"FORMAT/STANDARD,LIT/LIT,POS/BYTE2,CONST/@1,SHF/PASS.B,Q/UPDATE.Q"
;1837	Q <-- PASSB []000000		"FORMAT/STANDARD,LIT/LIT,POS/BYTE3,CONST/@1,SHF/PASS.B,Q/UPDATE.Q"
;1838
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   62
;     MACRO.MIC 	     SHIFT Macros									      /REV=
;
;1839
;1840	;	Shift macros, continued.
;1841
;1842	;	Shift macros with register operands with no destination.
;1843
;1844	NODST <-- [] LROT []		"FORMAT/STANDARD,LIT/BREG,VAL/@2,B/@1,A/@1,SHF/LEFT.DOUBLE"
;1845	NODST <-- [] LROT (SC)		"FORMAT/STANDARD,LIT/BREG,VAL/0,B/@1,A/@1,SHF/LEFT.DOUBLE"
;1846	NODST <-- [] RROT []		"FORMAT/STANDARD,LIT/BREG,VAL/@2,B/@1,A/@1,SHF/RIGHT.DOUBLE"
;1847	NODST <-- [] RROT (SC)		"FORMAT/STANDARD,LIT/BREG,VAL/0,B/@1,A/@1,SHF/RIGHT.DOUBLE"
;1848	NODST <-- []!![] LSH [] 	"FORMAT/STANDARD,LIT/BREG,VAL/@3,B/@2,A/@1,SHF/LEFT.DOUBLE"
;1849	NODST <-- []!![] LSH (SC)	"FORMAT/STANDARD,LIT/BREG,VAL/0,B/@2,A/@1,SHF/LEFT.DOUBLE"
;1850	NODST <-- []!![] RSH [] 	"FORMAT/STANDARD,LIT/BREG,VAL/@3,B/@2,A/@1,SHF/RIGHT.DOUBLE"
;1851	NODST <-- []!![] RSH (SC)	"FORMAT/STANDARD,LIT/BREG,VAL/0,B/@2,A/@1,SHF/RIGHT.DOUBLE"
;1852	NODST <-- []!![] RSH (32-SC)	"FORMAT/STANDARD,LIT/BREG,VAL/0,B/@2,A/@1,SHF/LEFT.DOUBLE"
;1853	NODST <-- SEXT [] RSH []	"FORMAT/STANDARD,LIT/BREG,VAL/@2,B/@1,A/SHIFT.SIGN,SHF/RIGHT.DOUBLE"
;1854	NODST <-- SEXT [] RSH (SC)	"FORMAT/STANDARD,LIT/BREG,VAL/0,B/@1,A/SHIFT.SIGN,SHF/RIGHT.DOUBLE"
;1855	NODST <-- SEXT [] RSH (32-SC)	"FORMAT/STANDARD,LIT/BREG,VAL/0,B/@1,A/SHIFT.SIGN,SHF/LEFT.DOUBLE"
;1856
;1857	NODST <-- PASSA []		"FORMAT/STANDARD,A/@1,SHF/PASS.A"
;1858	NODST <-- PASSB []		"FORMAT/STANDARD,LIT/BREG,B/@1,SHF/PASS.B"
;1859	NODST <-- 0			"FORMAT/STANDARD,SHF/PASS.Z"
;1860	NODST <-- [] LSH []		"FORMAT/STANDARD,LIT/BREG,VAL/@2,A/@1,SHF/LEFT.SINGLE"
;1861	NODST <-- [] LSH (SC)		"FORMAT/STANDARD,LIT/BREG,VAL/0,A/@1,SHF/LEFT.SINGLE"
;1862	NODST <-- ZEXT [] RSH []	"FORMAT/STANDARD,LIT/BREG,VAL/@2,B/@1,SHF/RIGHT.SINGLE"
;1863	NODST <-- ZEXT [] RSH (SC)	"FORMAT/STANDARD,LIT/BREG,VAL/0,B/@1,SHF/RIGHT.SINGLE"
;1864
;1865	;	Shift macros with constant operand with no destination.
;1866
;1867	NODST <-- PASSB K10.[]		"FORMAT/STANDARD,LIT/LIT,MISC/CONST.10.BIT,CONST.10/@1,SHF/PASS.B"
;1868	NODST <-- PASSB 000000[]	"FORMAT/STANDARD,LIT/LIT,POS/BYTE0,CONST/@1,SHF/PASS.B"
;1869	NODST <-- PASSB 0000[]00	"FORMAT/STANDARD,LIT/LIT,POS/BYTE1,CONST/@1,SHF/PASS.B"
;1870	NODST <-- PASSB 00[]0000	"FORMAT/STANDARD,LIT/LIT,POS/BYTE2,CONST/@1,SHF/PASS.B"
;1871	NODST <-- PASSB []000000	"FORMAT/STANDARD,LIT/LIT,POS/BYTE3,CONST/@1,SHF/PASS.B"
;1872
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   63
;     MACRO.MIC 	     SPECIAL Macros									      /REV=
;
;1873	.TOC	"	SPECIAL Macros"
;1874
;1875	FBOX OPERAND A[]		"FORMAT/SPECIAL,MISC1/FOP.VALID,DST/NONE,A/@1"
;1876	FBOX OPERAND A[] B[]		"FORMAT/SPECIAL,MISC1/FOP.VALID,DST/NONE,A/@1,LIT/BREG,B/@2"
;1877
;1878	RETIRE INSTRUCTION		"FORMAT/SPECIAL,MISC1/RETIRE.INSTRUCTION"
;1879	FLUSH VIC			"FORMAT/SPECIAL,MISC1/FLUSH.VIC"
;1880	FLUSH BRANCH PREDICTION TABLE	"FORMAT/SPECIAL,MISC1/FLUSH.BPC"
;1881	FLUSH PC QUEUE			"FORMAT/SPECIAL,MISC1/FLUSH.PCQ"
;1882
;1883	STATE.5-4 <-- 0 		"FORMAT/SPECIAL,MISC1/CLR.STATE.5-4"
;1884	STATE.3 <-- 1			"FORMAT/SPECIAL,MISC1/SET.STATE.3"
;1885	STATE.4 <-- 1			"FORMAT/SPECIAL,MISC1/SET.STATE.4"
;1886	STATE.5 <-- 1			"FORMAT/SPECIAL,MISC1/SET.STATE.5"
;1887
;1888	FBOX DEST CHECK 		"FORMAT/SPECIAL,LIT/BREG,MISC2/F.DEST.CHECK"
;1889	FLUSH PA QUEUE			"FORMAT/SPECIAL,LIT/BREG,MISC2/FLUSH.PAQ"
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   64
;     MACRO.MIC 	     Q, L, V Field Macros								      /REV=
;
;1890	.TOC	"	Q, L, V Field Macros"
;1891
;1892	Q&				"Q/UPDATE.Q"
;1893
;1894	LEN(DL) 			"L/LEN(DL)"
;1895	LONG				"L/LONG"
;1896
;1897	VA&				"V/UPDATE.VA"
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   65
;     MACRO.MIC 	     MISC Field Macros									      /REV=
;
;1898	.TOC	"	MISC Field Macros"
;1899
;1900	DL <-- BYTE			"MISC/DL.BYTE"
;1901	DL <-- WORD			"MISC/DL.WORD"
;1902	DL <-- LONG			"MISC/DL.LONG"
;1903	RESTART IBOX			"MISC/RESTART.IBOX"
;1904	RESTART MBOX			"MISC/RESTART.MBOX"
;1905	RESET CPU			"MISC/RESET.CPU"
;1906	STATE.3-0 <-- 0 		"MISC/CLR.STATE.3-0"
;1907	STATE.0 <-- 1			"MISC/SET.STATE.0"
;1908	STATE.1 <-- 1			"MISC/SET.STATE.1"
;1909	STATE.2 <-- 1			"MISC/SET.STATE.2"
;1910	SC <-- A []			"MISC/LOAD.SC.FROM.A,A/@1"
;1911	MPU <-- B.29..16 []		"MISC/LOAD.MPU.FROM.B,LIT/BREG,B/@1"
;1912	MULL				"MISC/MULL"
;1913	SET PSL CC.IIIP 		"MISC/LOAD.PSL.CC.IIIP"
;1914	SET PSL CC.IIII 		"MISC/LOAD.PSL.CC.IIII"
;1915	SET PSL CC.JIZJ 		"MISC/LOAD.PSL.CC.JIZJ"
;1916	SET PSL CC.IIIJ 		"MISC/LOAD.PSL.CC.IIIJ"
;1917	SET PSL CC.IIIP.QUAD		"MISC/LOAD.PSL.CC.IIIP.QUAD"
;1918	SET PSL CC.PPJP 		"MISC/LOAD.PSL.CC.PPJP"
;1919	CLEAR PMF COUNTERS		"MISC/CLR.PERF.COUNT"
;1920	INCREMENT PMF COUNTER		"MISC/INCR.PERF.COUNT"
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   66
;     MACRO.MIC 	     Microsequencer Control Macros							      /REV=
;
;1921	.TOC	"	Microsequencer Control Macros"
;1922
;1923	CALL CASE [] AT []		"SEQ.FMT/BRANCH,SEQ.CALL/CALL,SEQ.COND.1/<SEQ.COND/@1>,J/@2"
;1924	CASE [] AT []			"SEQ.FMT/BRANCH,SEQ.CALL/NOP,SEQ.COND.1/<SEQ.COND/@1>,J/@2"
;1925
;1926	RETURN				"SEQ.FMT/JUMP,SEQ.CALL/NOP,SEQ.MUX/STACK,J/0"
;1927
;1928	CALL [] 			"SEQ.FMT/JUMP,SEQ.CALL/CALL,SEQ.MUX/J,J/@1"
;1929	GOTO [] 			"SEQ.FMT/JUMP,SEQ.CALL/NOP,SEQ.MUX/J,J/@1"
;1930
;1931	LAST CYCLE			"SEQ.FMT/JUMP,SEQ.CALL/NOP,SEQ.MUX/LAST.CYCLE,J/0"
;1932	LAST CYCLE CHECK OVERFLOW	"SEQ.FMT/JUMP,SEQ.CALL/NOP,SEQ.MUX/LAST.CYCLE.OVERFLOW,J/0"
;1933	LAST CYCLE NO RETIRE		"FORMAT/SPECIAL,LIT/BREG,DISABLE.RETIRE/YES,SEQ.FMT/JUMP,SEQ.CALL/NOP,SEQ.MUX/LAST.CYCLE,J/0"
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   67
;     MACRO.MIC 	     A/B Select Macros									      /REV=
;
;1934	.TOC	"	A/B Select Macros"
;1935
;1936	;	The A/B Select macros provide a way to explicitly specify an A or B port select.
;1937
;1938	ACCESS A []			"A/@1"
;1939	ACCESS B []			"LIT/BREG,B/@1"
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   68
;     MACRO.MIC 	     Error Macros									      /REV=
;
;1940	.TOC	"	Error Macros"
;1941
;1942	;	These macros provide standard entries to microcode error routines.
;1943
;1944	CONSOLE HALT [] 		"[SAVEPSL] <-- [PSL] OR 0000[@1]00,LONG,GOTO [IE.CONSOLE.HALT..]"
;1945	CONSOLE HALT NO CLEANUP []	"[SAVEPSL] <-- [PSL] OR 0000[@1]00,LONG,GOTO [IE.CONSOLE.HALT.NO.CLEANUP..]"
;1946	MACHINE CHECK []		"[SAVEPSL] <-- 00[@1]0000,LONG,GOTO [IE.MACHINE.CHECK..]"
;1947	RESERVED OPERAND FAULT		"GOTO [IE.RSVD.OPERAND..]"
;1948	RESERVED INSTRUCTION FAULT	"GOTO [RSVD.OPCODE..]"
;1949	RESERVED ADDRESSING MODE	"GOTO [IE.RSVD.ADDRESS..]"
;1950	INTERRUPT FAULT 		"GOTO [IE.INT.FAULT..]"
;1951	UNIMPLEMENTED MTPR REGISTER []	"[W2] <-- [@1] LSH [2.],LONG,GOTO [MTPR.IPR.NORMAL]"
;1952	UNIMPLEMENTED MFPR REGISTER []	"[W2] <-- [@1] LSH [2.],LONG,GOTO [MFPR.IPR.NORMAL]"
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   69
;     MACRO.MIC 	     Simulator Control Macros								      /REV=
;
;1953	.TOC	"	Simulator Control Macros"
;1954
;1955	;	These macros control simulator features that do not exist in the real hardware
;1956
;1957	;	Address selection macros.
;1958
;1959	sim addr []			"SIM.ADDR.SEL/ADDR,SIM.ADDR/@1"
;1960	sim addr [] - k 		"SIM.ADDR.SEL/ADDR.K,SIM.ADDR/@1"
;1961	sim addr [] + k 		"SIM.ADDR.SEL/ADDR.K,SIM.ADDR/@1"
;1962
;1963	;	Microbranch condition selection macros.
;1964
;1965	sim cond k s3.[]		"SIM.COND.SEL/CONST,SIM.COND.S3.S4/S3,SIM.COND.K/@1"
;1966	sim cond k s4.[]		"SIM.COND.SEL/CONST,SIM.COND.S3.S4/S4,SIM.COND.K/@1"
;1967	sim cond []			"SIM.COND.SEL/FNC,SIM.COND/@1"
;1968
;1969	;	Simulator control macros.
;1970
;1971	sim halt			"MISC/SIM.HALT"
;1972	sim ie.intexc			"MISC/SIM.IE.INTEXC"
;1973	sim exception			"SIM.CTRL/CMD,SIM.CMD/EXCEPTION"
;1974	sim rsvd opcode 		"SIM.CTRL/CMD,SIM.CMD/RSVD.OPCODE"
;1975	sim emulate			"SIM.CTRL/CMD,SIM.CMD/EMULATE"
;1976	sim vector fault		"SIM.CTRL/CMD,SIM.CMD/VECTOR.FAULT"
				;1977	.bin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   70
;     ALIGN.MIC 	     ALIGN.MIC -- Hardware Entry Point Assignments					      /REV=
;
				;1978	.TOC	"ALIGN.MIC -- Hardware Entry Point Assignments"
				;1979	.TOC	"Revision 1.0"
				;1980
				;1981	;	Mike Uhler, Bob Supnik
				;1982
;1983	.nobin
;1984	;****************************************************************************
;1985	;*									    *
;1986	;*  COPYRIGHT (c) 1988, 1989, 1990, 1991, 1992 BY			    *
;1987	;*  DIGITAL EQUIPMENT CORPORATION, MAYNARD, MASSACHUSETTS.		    *
;1988	;*  ALL RIGHTS RESERVED.						    *
;1989	;*									    *
;1990	;*  THIS SOFTWARE IS FURNISHED UNDER A LICENSE AND MAY BE USED AND COPIED   *
;1991	;*  ONLY IN  ACCORDANCE WITH  THE  TERMS  OF  SUCH  LICENSE  AND WITH THE   *
;1992	;*  INCLUSION OF THE ABOVE COPYRIGHT NOTICE.  THIS SOFTWARE OR ANY  OTHER   *
;1993	;*  COPIES THEREOF MAY NOT BE PROVIDED OR OTHERWISE MADE AVAILABLE TO ANY   *
;1994	;*  OTHER PERSON.  NO TITLE TO AND OWNERSHIP OF  THE  SOFTWARE IS  HEREBY   *
;1995	;*  TRANSFERRED.							    *
;1996	;*									    *
;1997	;*  THE INFORMATION IN THIS SOFTWARE IS  SUBJECT TO CHANGE WITHOUT NOTICE   *
;1998	;*  AND  SHOULD  NOT  BE  CONSTRUED AS	A COMMITMENT BY DIGITAL EQUIPMENT   *
;1999	;*  CORPORATION.							    *
;2000	;*									    *
;2001	;*  DIGITAL ASSUMES NO RESPONSIBILITY FOR THE USE  OR  RELIABILITY OF ITS   *
;2002	;*  SOFTWARE ON EQUIPMENT WHICH IS NOT SUPPLIED BY DIGITAL.		    *
;2003	;*									    *
;2004	;****************************************************************************
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   71
;     ALIGN.MIC 	     Revision History									      /REV=
;
;2005	.TOC	"	Revision History"
;2006
;2007	; Edit	  Date	 Who	     Description
;2008	; ---- --------- ---	---------------------
;2009	; (1)0 01-Aug-90 GMU	Initial production microcode.
;2010	;
;2011	; Begin version 1.0 here
;2012	;   16 31-JUL-90 GMU	Add constraints for NVAX+ vector entry points.
;2013	;   15 20-Jun-90 DGM	Fix FQ alignment constraints
;2014	;   14 26-Apr-90 GMU	Convert '*' fill constraints to 'x' constraints.
;2015	;   13 13-Mar-90 GMU	With the cancellation of SVS, remove the PROBEVMX..
;2016	;			entry point.
;2017	;   12 05-Mar-90 GMU	Duplicate individual field queue constraints to keep
;2018	;			ARCS from complaining about the use of the middle of
;2019	;			an ALIGNLIST as a branch target.
;2020	;   11 16-Jan-90 DGM	Change field queue alignments.
;2021	;   10 05-Jan-90 GMU	Remove vector issue microtrap constraint, collapse other
;2022	;			entry point addresses.
;2023	;    9 06-Dec-89 GMU	Continue comment update.
;2024	;    8 30-Nov-89 GMU	Combine ADWC, SBWC entry points, move EDIV.
;2025	;    7 28-Nov-89 GMU	Update microtrap addresses to reflect new hardware priority.
;2026	;    6 27-Sep-89 DGM	Modify alignment constraints on EDIV.  (remove .R & .M)
;2027	;    5 17-Aug-89 GMU	Update to reflect new field queue entry points.
;2028	;    4 24-Jul-89 GMU	Add new exception entry points.
;2029	;    3 07-Dec-88 DB	Redo floating point entry points, add FBOX.4.SL.ND..
;2030	;    2 06-Dec-88 DB	Redo floating point entry points
;2031	;    1 22-Nov-88 DB	Add new floating point entry points
;2032	; (0)0 16-Feb-88 RMS	Trial microcode.
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   72
;     ALIGN.MIC 	     Revision History									      /REV=
;
;2033
;2034	;				ALLOCATION NOTE
;2035	;
;2036	;	Unlike previous instances of microcode allocators, the NVAX allocator
;2037	;	responds to four types of constraints:
;2038	;
;2039	;		0	Address bit is constrained to a 0.
;2040	;		1	Address bit is constrained to a 1.
;2041	;		*	Address bit is logically unconstrained,
;2042	;			but is forced to be constrained to a 1.
;2043	;		x	Address bit is unconstrained.
;2044	;
;2045	;	The addition of the 'x' constraint and the redefinition of the '*'
;2046	;	constraint was done to lessen the chance that the microcoder has
;2047	;	misanalyzed the constraint requirements by forcing the constraint
;2048	;	to a '1'.  Unfortunately, this causes congestion in addresses whose
;2049	;	lower address bits are a 1 to such an extent that the microcode
;2050	;	will not allocate entirely within the range 0..1599.  As such,
;2051	;	all ALIGNLISTs have been categorized into "safe" and "unsafe"
;2052	;	constraints.  "Safe" constraints are those that are judged to be
;2053	;	unlikely to be wrong (an opcode case is considered a "safe"
;2054	;	constraint).  "Unsafe" constraints are those where the logic is
;2055	;	complex enough that there is a non-zero chance that the constraint
;2056	;	could be wrong.  "Safe" constraints have been changed from '*'
;2057	;	constraints to 'x' constraints, while "unsafe" constraints remain
;2058	;	'*' constraints.
;2059
				;2060	.bin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   73
;     ALIGN.MIC 	     Exception Dispatches								      /REV=
;
				;2061	.TOC	"	Exception Dispatches"
				;2062
				;2063	;	Exception dispatches are placed in page 0 of the
				;2064	;	Control Store, as follows:
				;2065	;
				;2066	;		 10  9	8  7  6  5  4  3  2  1	0
				;2067	;		+--+--+--+--+--+--+--+--+--+--+--+
				;2068	;		|0  0  0 |    dispatch	   |0  0 |
				;2069	;		+--+--+--+--+--+--+--+--+--+--+--+
				;2070	;
				;2071	;	where
				;2072	;
				;2073	;		dispatch =	dispatch address from the trap hardware
				;2074	;
				;2075	;	Note: The following entry points are spaced 4 locations apart to
				;2076	;	allow more than one CALL at each entry point.  Entry points starting
				;2077	;	with IE.CONSOLE.HALT.. are not constrained by hardware requirement,
				;2078	;	but are constrained such that exception handler addresses are
				;2079	;	constant for all microcode assemblies.
				;2080
				;2081	;= AT 0
				;2082	;= ALIGNLIST 00000xx	(
				;2083	;= IE.POWERUP..,	IE.ASYNC.HW.ERROR..,
				;2084	;= IE.INT.OVERFLOW..,	IE.BRANCH..,
				;2085	;= IE.RSVD.OPCODE.TRAP..,IE.SYNC.HW.ERROR..,
				;2086	;= IE.MEMMGT.., 	IE.RSVD.ADDRESS..,
				;2087	;= IE.FLT.FAULT..,	IE.INT..,
				;2088	;= IE.TRACE.TRAP..,	IE.FPD..,
				;2089	;= IE.STALL..,		IE.CONSOLE.HALT..,
				;2090	;= IE.MACHINE.CHECK..,	IE.RSVD.OPERAND..,
				;2091	;= IE.INT.FAULT..,	IE.SUBSCRIPT.ERROR..,
				;2092	;= IE.DIVIDE.ERROR..,		 )
				;2093
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   74
;     ALIGN.MIC 	     Instruction Dispatches								      /REV=
;
				;2094	.TOC	"	Instruction Dispatches"
				;2095
				;2096	;	Instruction dispatches are placed in pages 1, 2, and 3 of the
				;2097	;	Control Store, as follows:
				;2098	;
				;2099	;		 10  9	8  7  6  5  4  3  2  1	0
				;2100	;		+--+--+--+--+--+--+--+--+--+--+--+
				;2101	;		|  page  |	 dispatch     |0 |
				;2102	;		+--+--+--+--+--+--+--+--+--+--+--+
				;2103	;
				;2104	;	where
				;2105	;
				;2106	;		page	=	001: instructions with no first cycle constraints
				;2107	;			=	010: instructions with mild first cycle constraints
				;2108	;			=	011: MxPR
				;2109	;		dispatch =	dispatch address from the IPLA
				;2110	;
				;2111	;	Note: The following entry points are spaced 2 locations apart to
				;2112	;	allow a CALL at each entry point.  Changes to these entry points
				;2113	;	require a reassembly of the IROM.
				;2114	;
				;2115	;	Page 1 - instructions with no first cycle constraints.
				;2116
				;2117	;= AT 100
				;2118	;= ALIGNLIST 000000x	(
				;2119	;= RSVD.OPCODE..,TSTX..,	BITX.., 	CMPI..,
				;2120	;= MOVX..,	MOVQ.., 	CLRX.., 	CLRQ..,
				;2121	;= MOVZBX..,	MOVZWL..,	MCOMX..,	MNEGX..,
				;2122	;= ADDIN..,	SUBIN..,	ADWC.SBWC..,		,
				;2123	;= INCX..,	DECX.., 		,		,
				;2124	;= BISXN..,	BICXN..,	XORXN..,		,
				;2125	;= CVTBI..,	CVTWL..,	CVTLW..,	CVTXB..,
				;2126	;= ROTL..,	ASHL.., 	ASHQ.., 		,
				;2127	;= SOBGXX..,	AOBLXX..,		,		,
				;2128	;= ACBB..,	ACBW.., 	ACBL.., 		,
				;2129	;= BSBX..,	JSB..,		RSB..,		CASEX..,
				;2130	;= BRX..,	BXX..,		BLBX.., 	JMP..,
				;2131	;= MULBN..,	MULWN..,	MULLN..,	EMUL..,
				;2132	;= DIVBN..,	DIVWN..,	DIVLN..,	EDIV..,
				;2133	;= CALLX..,	RET..,			,		,
				;2134	;=	,		,		,		)
				;2135
				;2136	;= AT 180
				;2137	;= ALIGNLIST 000000x	(
				;2138	;= NOP..,	HALT.., 	BPT..,		XFC..,
				;2139	;= INDEX..,	MOVPSL..,	PUSHR..,	POPR..,
				;2140	;= INSQUE..,	REMQUE..,	INSQXI..,		,
				;2141	;= REI..,		,		,		,
				;2142	;= LOCC.SKPC.., SCANC.SPANC..,		,		,
				;2143	;= FBOX.1.SL.., FBOX.2.SL..,	FBOX.4.SL..,		,
				;2144	;= FBOX.1.SL.ND..,FBOX.2.SL.ND..,FBOX.4.SL.ND..,	,
				;2145	;= EMULATE.4.., EMULATE.5..,	EMULATE.6..,		,
				;2146	;= VLDX..,		,	VSTX.., 		,
				;2147	;= VGATHX..,		,	VSCATX..,		,
				;2148	;= MFVP..,		,	MTVP.., 		,
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   75
;     ALIGN.MIC 	     Instruction Dispatches								      /REV=
;
				;2149	;= VSYNC..,		,	IOTA.., 		,
				;2150	;= VVOPX..,		,	VVCMPX..,		,
				;2151	;= VSOPL..,		,	VSCMPL..,		,
				;2152	;= VSOPQ..,		,	VSCMPQ..,		,
				;2153	;=	,		,		,		)
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   76
;     ALIGN.MIC 	     Instruction Dispatches								      /REV=
;
				;2154
				;2155	;	Page 2 - instructions with mild first cycle constraints.
				;2156
				;2157	;	The alignments for CVTPL.., BBX.., BBXS.., BBXC..,
				;2158	;	REMQXI.., ADAWI.., FIELD.., and INSV.. reflect the restrictions
				;2159	;	imposed by the field queue case constraints.  These alignments
				;2160	;	must not be changed relative to the coresponding .M and .R
				;2161	;	labels.
				;2162
				;2163	;= AT 200
				;2164	;= ALIGNLIST 000000x	(
				;2165	;= BIXPSW..,	MOVCX..,	CMPCX..,		,
				;2166	;= LDPCTX..,	SVPCTX..,	PROBEX..,		,
				;2167	;= CHMK..,	CHME.., 	CHMS.., 	CHMU..,
				;2168	;=	,		,		,		,
				;2169	;=	,		,		,		,
				;2170	;=	,		,		,		,
				;2171	;=	,		,		,		,
				;2172	;=	,		,		,		)
				;2173
				;2174	;	The following ALIGNLISTS must be separate from the above ALIGNLIST
				;2175	;	because the microcode analyzer ARCS does not like to see case targets
				;2176	;	in the middle of an ALIGNLIST nor as the beginning of a large
				;2177	;	ALIGNLIST.  Logically, this group of ALIGNLISTs belongs at the
				;2178	;	end of the large ALIGNLIST above.
				;2179
				;2180	;= AT 240
				;2181	;= ALIGNLIST 00x (ADAWI.M,	ADAWI.R,		,	ADAWI..,)
				;2182	;= AT 248
				;2183	;= ALIGNLIST 00x (BBX.M,	BBX.R,			,	BBX..)
				;2184	;= AT 250
				;2185	;= ALIGNLIST 00x (BBXS.M,	BBXS.R, 		,	BBXS..)
				;2186	;= AT 258
				;2187	;= ALIGNLIST 00x (BBXC.M,	BBXC.R, 		,	BBXC..)
				;2188	;= AT 260
				;2189	;= ALIGNLIST 00x (FIELD.M,	FIELD.R,		,	FIELD..)
				;2190	;= AT 268
				;2191	;= ALIGNLIST 00x (INSV.M,	INSV.R, 		,	INSV..)
				;2192	;= AT 270
				;2193	;= ALIGNLIST 00x (REMQXI.M,	REMQXI.R,		,	REMQXI..)
				;2194	;= AT 278
				;2195	;= ALIGNLIST 00x (EMULATE.3.CVTPL.M..,	CVTPL.R,	,	CVTPL..)
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   77
;     ALIGN.MIC 	     Instruction Dispatches								      /REV=
;
				;2196
				;2197	;	Page 3 - MxPR.
				;2198
				;2199	;= AT 300
				;2200	;= ALIGNLIST 0x (MTPR..,	MFPR..)
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   78
;   POWERUP.MIC 	     POWERUP.MIC -- Powerup Initialization						      /REV=
;
				;2201	.TOC	"POWERUP.MIC -- Powerup Initialization"
				;2202	.TOC	"Revision 1.5"
				;2203
				;2204	;	Mike Uhler, Bob Supnik, John Brown
				;2205
;2206	.nobin
;2207	;****************************************************************************
;2208	;*									    *
;2209	;*  COPYRIGHT (c) 1987, 1988, 1989, 1990, 1991, 1992 BY 		    *
;2210	;*  DIGITAL EQUIPMENT CORPORATION, MAYNARD, MASSACHUSETTS.		    *
;2211	;*  ALL RIGHTS RESERVED.						    *
;2212	;*									    *
;2213	;*  THIS SOFTWARE IS FURNISHED UNDER A LICENSE AND MAY BE USED AND COPIED   *
;2214	;*  ONLY IN  ACCORDANCE WITH  THE  TERMS  OF  SUCH  LICENSE  AND WITH THE   *
;2215	;*  INCLUSION OF THE ABOVE COPYRIGHT NOTICE.  THIS SOFTWARE OR ANY  OTHER   *
;2216	;*  COPIES THEREOF MAY NOT BE PROVIDED OR OTHERWISE MADE AVAILABLE TO ANY   *
;2217	;*  OTHER PERSON.  NO TITLE TO AND OWNERSHIP OF  THE  SOFTWARE IS  HEREBY   *
;2218	;*  TRANSFERRED.							    *
;2219	;*									    *
;2220	;*  THE INFORMATION IN THIS SOFTWARE IS  SUBJECT TO CHANGE WITHOUT NOTICE   *
;2221	;*  AND  SHOULD  NOT  BE  CONSTRUED AS	A COMMITMENT BY DIGITAL EQUIPMENT   *
;2222	;*  CORPORATION.							    *
;2223	;*									    *
;2224	;*  DIGITAL ASSUMES NO RESPONSIBILITY FOR THE USE  OR  RELIABILITY OF ITS   *
;2225	;*  SOFTWARE ON EQUIPMENT WHICH IS NOT SUPPLIED BY DIGITAL.		    *
;2226	;*									    *
;2227	;****************************************************************************
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   79
;   POWERUP.MIC 	     Revision History									      /REV=
;
;2228	.TOC	"	Revision History"
;2229
;2230	; Edit	  Date	 Who	     Description
;2231	; ---- --------- ---	---------------------
;2232	;    5 09-Jan-92 JFB	Symptom: additional microword for edit 4 causes
;2233	;				 undesired reallocation for the mini-pass.
;2234	;			Cure:	 change order and tie down the single instruction
;2235	;				 that clears the PCSTS lock bit.
;2236	;    4 24-Jul-91 JFB	Symptom: In the burnin flow, the Pcache is enabled
;2237	;				 without clearing the lock bit in the PCSTS.
;2238	;				 This disables the Pcache regardless of the
;2239	;				 state of PCCTL.
;2240	;			Cure:	 Write a 1 to PCSTS to clear the lock bit
;2241	;				 before enabling the Pcache via PCCTL.
;2242	;    3 14-Jun-91 GMU	Symptom: When MAPEN is cleared in the console halt
;2243	;				 flow, the VIC can still have valid data
;2244	;				 corresponding to virtual addresses that
;2245	;				 matched the physical addresses in which
;2246	;				 the console is running (with the S1 space
;2247	;				 ECO, E0040000 is a valid S0 space virtual
;2248	;				 address).  This could cause the CPU to
;2249	;				 start executing bogus instructions rather
;2250	;				 than the console code.
;2251	;			Cure:	 Flush the VIC after turning off MAPEN in
;2252	;				 the console halt flow and before restarting
;2253	;				 prefetch.
;2254	;    2 20-May-91 GMU	Symptom: Certain console halts may be invoked from
;2255	;				 flows in which a RESET CPU and call to
;2256	;				 IE.CLEANUP.CPU have been performed.  If
;2257	;				 this call packs up the state for a string
;2258	;				 instruction, a second RESET CPU and call
;2259	;				 to IE.CLEANUP leaves SAVEPSL with FPD
;2260	;				 set and SAVEPC pointing at the instruction
;2261	;				 following the string instruction rather than
;2262	;				 at the string instruction.
;2263	;			Cure:	 Add an alternate console halt entry point,
;2264	;				 IE.CO